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timplatt
Participant
Participant
3,423 Views
Registered: ‎02-03-2010

constant sample time not inf & which solver to use?

I have a very simple SysGen design.

 

A file input fed to a Xilinx input and is added to a constant using the AddSub block.

This result is fed to Xilinx output and displayed on a scope.

 

The system generator block has a FPGA clock period of 1/(simfs*1e6)*1e9          (simfs = 80)   (i.e. the design is intended to run at 80 MHz)

The system generator block Simulink period = 1/(simfs*1e6)

 

 BTW, this is a cut out of a larger design which I have working to some extent.

 

Question 1) Which solver do I use?  I would expect that the discrete solver with a fixed step makes the most sense.

However, things only work with a variable step.  I saw this in one of Xilinx's app notes but haven't found it in the primary

documentation.  (I do see that the xlConfigureSolver mentions SolverType = Variable-Step, Solver = VariableStepDiscrete

but doesn't say this is required.

 

Question 2) When I run this simple model (discrete solver, variable-step) and look at the sample times of the signals

I get the following:

 

- file block out = 1.25e-8       note: this is set in the sample time of the block parameters

- in port = 1.25e-8

- constant block out = 5.2429e-9    !!!!????

- addsub block out = 5.2429e-9

- out port = 1.25e-8   ???

 

 Why is the constant block 5.2429e-9?  Where did this value come from?  Why isn't it infinity?

 

Note that if I delete the constant block and re-add it and hit "Update diagram" icon in Simulink, the sample time does go to infinity (as expected)

and the 5.2429e-9 goes away.

 

However, running the model brings the 5.2429e-9 back.

 

What is going on here?  

 

This 5.2429e-9 keeps getting in the way when I try to add other pieces to the design because I

keep running into the non-integer multiple problem.     (5.2429e-9 is not an integer multiple of the fundamental clock / sample time of 1.25e-8)

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jeffreyh
Xilinx Employee
Xilinx Employee
3,158 Views
Registered: ‎08-07-2007

The variable step solver should be used.

 

It is possible to see different rates displayed after a simulation vs. after a model update (Ctrl-d).  See AR 30131 for details on this behavior:

http://www.xilinx.com/support/answers/30131.htm

 

This is a result of the way the SysGen solver interacts with the Simulink solver for simulating the design.  The correct rate, which will be used during HDL generation is that which is displayed after a model update.

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