cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Gloria_gao
Participant
Participant
721 Views
Registered: ‎11-15-2020

csi rx has no stream on ila

Jump to solution

Hi,I am using mipi csi-2 rx ip to receive the data from IMX219, however, from the ila, there is no stream.

In vitis, I have iic initialization, sensor initialization, csi initalization and enable csi. When I debug, I find that the programm is stuck in enable csi().

What is the problem?

The block design, the ip configuration and the vitis part will be provided as attachments.

In the project, the sensor configuration has been tested successfully.

Thank you!

main.png
CSI IP.png
0 Kudos
1 Solution

Accepted Solutions
karnanl
Xilinx Employee
Xilinx Employee
479 Views
Registered: ‎03-30-2016

Hello @Gloria_gao 

>Are the lp for clk lanes neccessary?

Yes, you need to connect all these ports.


>Are there any documents for the function of lp lanes (data lanes and clk lanes)?

Please check PG202 Chapter 2 for MIPI PHY ports explanation.
DPHY_IF_TABLE16.png

Kind regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post

12 Replies
florentw
Moderator
Moderator
693 Views
Registered: ‎11-09-2015

Hi @Gloria_gao 

I am not sure if you can use a clock coming from the Zynq PS for the dphy_clk_200M. Do you have any on-board clock you can use?

Are you sure clk2 is set to 250MHz (because the Processor reset name has 99MHz)?

You might want to add an ILA on the AXI4-lite interface and check what transactions are happening.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Gloria_gao
Participant
Participant
679 Views
Registered: ‎11-15-2020

Hi, there are no other clk on the board (TE0726) that I can use. The csi ip provided by TE0726 example work well and the clock is also from ps.  However, I would like to use the csi ip provided by xilinx. But I am not sure whether clock for dphy can be from ps.

I have seen a post that mentioned that the video clk should be greater than dphy clk? Is it right? According to the user guide of CSI RX IP, the clk2 >= 182.4 Mhz will be enough. I do not know why Processor reset name has 99MHz.

What axi-lite interface do you point?

By the way, I do not understand the active lanes. If I disable the active lanes, the data lanes will be the number selected in "serial data lanes"?

If I enable the active lanes and the serial data lanes is 2, the data lanes in work could be 1 or 2 by configuring active lanes? Is it right?

If I want to have 2 data lanes in work, can I select 2 in "serial data lanes" and disable active lanes?

 

0 Kudos
watari
Professor
Professor
615 Views
Registered: ‎06-16-2013

Hi @Gloria_gao 

 

Unfortunately, Zynq (not Zynq MPSoC) can't directly receive MIPI signals.

And, I guess Trenz's example design properly treats it.

 

So, you have to make sure IO structure for HS and LP and properly implement it.

 

Hope this helps,

 

Best regards,

karnanl
Xilinx Employee
Xilinx Employee
589 Views
Registered: ‎03-30-2016

Hello @Gloria_gao 

I tried to check Trenz TE0726 board documents below
https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/special/TE0726/REV03/Documents 

It seems @watari advise is correct that Trenz TE0726 board does not have a proper resistor network to receive MIPI D-PHY signal.
(See picture below, please notice that CSI_D1 and CSI_C signals are connected directly to 7-series Zynq device.)
No_resistor_network_on_board.png

7-series devices IO does not have a native support MIPI D-PHY signal.
So if you are using Xilix MIPI CSI-2 RX IP,  you will need additional PHY device ( from Meticom etc), or resistor network described in XAPP894 to receive MIPI D-PHY signal.

Kind regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------
Gloria_gao
Participant
Participant
568 Views
Registered: ‎11-15-2020

Thank you!

0 Kudos
Gloria_gao
Participant
Participant
567 Views
Registered: ‎11-15-2020

Thanks, 

But the example provided by TE0726 also include the dphy ip. It seems to be that TE0726 also support mipi signal. Is this ip different from the MIPI DPHY specifications? The block is provided as attachment. (The block design has been tested and the video can display on the monitor correctly).

Besides, the constrains provided by the example are listed below:

#csi
set_property PACKAGE_PIN N11 [get_ports clk_rxp_0]
set_property IOSTANDARD LVDS_25 [get_ports clk_rxp_0]
set_property PACKAGE_PIN M9 [get_ports {data_lp_n_0}]
set_property IOSTANDARD HSUL_12 [get_ports {data_lp_n_0}]
set_property PACKAGE_PIN N9 [get_ports {data_lp_p_0}]
set_property IOSTANDARD HSUL_12 [get_ports {data_lp_p_0}]
set_property PACKAGE_PIN M10 [get_ports {data_rxp_0[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {data_rxp_0[0]}]
set_property PACKAGE_PIN P13 [get_ports {data_rxp_0[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {data_rxp_0[1]}]
set_property INTERNAL_VREF 0.6 [get_iobanks 34]

set_property PULLDOWN true [get_ports {data_lp_p_0}]
set_property PULLDOWN true [get_ports {data_lp_n_0}]

0 Kudos
watari
Professor
Professor
556 Views
Registered: ‎06-16-2013

Hi @Gloria_gao 

 

As you might know, pin N11, M10 and so on are for HS and M9 and N9 are for LP.

So, you have to properly connect these signals for HS and LP.

 

Best regards,

Gloria_gao
Participant
Participant
536 Views
Registered: ‎11-15-2020

Hi @watari 

I understand what you mean. In the example provided by Te0726, the pin N11, M10, M9 and N9 are connected to the csi ip provided by te0726

2.png

 

it seems that the ip has the mipi ppi signal. So my question is that whether the csi ip provided by xilinx can replace the csi_d_phy_rx ip+ csi_to_axis ip provided by TE0726 directly?

 

Thanks for your reply!

karnanl
Xilinx Employee
Xilinx Employee
508 Views
Registered: ‎03-30-2016

Hello @Gloria_gao 

I can see now Trenz is providing a custom MIPI CSI-2 RX IP for their boards.
This IP only requires data_lane0 LP signal.

TRENZ_BOARD.png

Xilinx MIPI CSI-2 RX Subsystem requires LP signal for clock lane and all data lanes.
So, unfortunately Xilinx MIPI IP will not work on your Trenz board,
You need to use their IP in this case.


Kind regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------
Gloria_gao
Participant
Participant
503 Views
Registered: ‎11-15-2020

Hi, @karnanl 

It seems that if I select one data lanes, the lp for data lanes can be solved. But the problem of the lp for clk lanes still exists. Are the lp for clk lanes neccessary?

Are there any documents for the function of lp lanes (data lanes and clk lanes)? I can not find relevant materials in user guide of CSI RX IP.

0 Kudos
karnanl
Xilinx Employee
Xilinx Employee
480 Views
Registered: ‎03-30-2016

Hello @Gloria_gao 

>Are the lp for clk lanes neccessary?

Yes, you need to connect all these ports.


>Are there any documents for the function of lp lanes (data lanes and clk lanes)?

Please check PG202 Chapter 2 for MIPI PHY ports explanation.
DPHY_IF_TABLE16.png

Kind regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post

Gloria_gao
Participant
Participant
432 Views
Registered: ‎11-15-2020

Thank you!  (●'◡'●)