I have to insert my video processing system in my vivado project with VDMA and Axis-Stream to Video Out, basically , from what I understand now , I have to have a block with a s_axis_video and m_axis_video, I have followed UG934, and I based myself in a project with a DMA and a custom FIFO AXis stream , where I add the block to generate EOL and SOF , and tried to follow the template that the UG934 shows.
entity axis_fifovid_v1_0 is
generic (
-- Users to add parameters here
ADDR_WIDTH : integer := 12;
C_AXIS_TDATA_WIDTH : integer := 24;
-- User parameters ends
-- Do not modify the parameters beyond this line
C_S0_DATA_WIDTH : integer := 24;
C_S0_VIDEO_FORMAT : integer := 2;
C_S0_AXIS_TDATA_WIDTH : integer := 24;
C_S0_MAX_SAMPLES_PER_CLOCK : integer := 1;
C_M0_DATA_WIDTH : integer := 24;
C_M0_VIDEO_FORMAT : integer := 2;
C_M0_AXIS_TDATA_WIDTH : integer := 24;
C_M0_MAX_SAMPLES_PER_CLOCK : integer := 1
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXIS
s_axis_video0_aclk : in std_logic;
s_axis_video0_aresetn : in std_logic;
s_axis_video0_tready : out std_logic;
s_axis_video0_tdata : in std_logic_vector(C_S0_DATA_WIDTH-1 downto 0);
s_axis_video0_tlast : in std_logic;
s_axis_video0_tuser : in std_logic;
s_axis_video0_tvalid : in std_logic;
-- Ports of Axi Master Bus Interface M00_AXIS
m_axis_video0_aclk : in std_logic;
m_axis_video0_aresetn : in std_logic;
m_axis_video0_tvalid : out std_logic;
m_axis_video0_tdata : out std_logic_vector(C_M0_DATA_WIDTH-1 downto 0);
m_axis_video0_tlast : out std_logic;
m_axis_video0_tuser : out std_logic;
m_axis_video0_tready : in std_logic
);
end axis_fifovid_v1_0;
so UG934 says : "
The Video to AXI4-Stream and AXI4-Stream to
Video cores are delivered as HDL source
code and provided as examples to expedite custom interface development
"but I haven't found this HDL source yet ... so someone has any tip about such systems (custom IP)
or examples of S_AXIS_VIDEO M_AXIS_VIDEO interfaces ... please.
