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Registered: ‎01-27-2011

empty and full flag assert simultaneous for FIFO from System Generator

I used a FIFO in System Generator, and generated the netlist. Then used ISE to generate the bit stream.

I found that the result was not stable. If the bit file is generated for sevral times, in some of these results, the empty and full flag assert simultaneous for FIFO, and whole design failed to work.


BTW. In my design, the read and write ports of the FIFO used the same clock, and all timing constrains were met. The ISE tool is 12.4, and Matlab is 2010b.


Did any one meet the same problem? How to solve it?


Thanks in advanced.





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Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2007

This isn't normal, but things to look at:


Does it work this way in software simulation?  If so then check the FIFO settings.  Maybe your FIFO isn't configured properly.


Are you trying to read the flags in sysgen, while the clock in hardware is free running?  If so then this will not work as they hardware is working so much faster than software that you may end up with strage results.  You should try the single-step simulation.



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