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Contributor
3,955 Views
Registered: ‎11-26-2010

fftshift using system generator

hi

To shift the zero frequency component towards center we use fftshift command in matlab.

But I was unable to find any block for this in system generator.

So I want to ask do Ihave to write the whole algorithm to implement this or is there any other way.

SALMAN

1 Solution

Accepted Solutions
Xilinx Employee
4,362 Views
Registered: ‎02-09-2009

Hi,

There is no dedicated block in system generator that will implement the fftshift function. To implement this, again it is just about how you read from memory. The most straight forward way is to write the results in Block RAM, then read the results in the order that the fftshift will output. You would have to wait until 1/2 of the FFT result is written, then for example for a 1024pt fft, start reading from 513-1024, then 1-512. You just have to build an address generator that addresses the Block RAM this way from counters/comparators etc.

One thing to think about, the FFT algorithm will initially output the results in bit-reversed order. Internally, there is a Block RAM buffer that is used to re-order the results into natural order (1-n). This buffereing is optional and adds latency. At the expense of a more complicated address generator, you can take the bit-reversed output of the fft and directly re-order the output so DC is in the center as the fftshift function does. This would reduce the amount of memory required and reduce latency, but require a bit more complex control logic.

Cheers,

-es

Xilinx Employee
4,363 Views
Registered: ‎02-09-2009

Hi,

There is no dedicated block in system generator that will implement the fftshift function. To implement this, again it is just about how you read from memory. The most straight forward way is to write the results in Block RAM, then read the results in the order that the fftshift will output. You would have to wait until 1/2 of the FFT result is written, then for example for a 1024pt fft, start reading from 513-1024, then 1-512. You just have to build an address generator that addresses the Block RAM this way from counters/comparators etc.

One thing to think about, the FFT algorithm will initially output the results in bit-reversed order. Internally, there is a Block RAM buffer that is used to re-order the results into natural order (1-n). This buffereing is optional and adds latency. At the expense of a more complicated address generator, you can take the bit-reversed output of the fft and directly re-order the output so DC is in the center as the fftshift function does. This would reduce the amount of memory required and reduce latency, but require a bit more complex control logic.

Cheers,

-es