cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
1,232 Views
Registered: ‎07-26-2018

hdmi pass through

Jump to solution

Hello, I try to hdmi pass through using these documantation https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-z7-hdmi-in-demo and https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-z7-hdmi-demo/start. 

But i have no iade hown can i use bot of them? how to connect blocks? I want to take the stream from the computer and give it to the monitor.  Can i use these ip without processing system, only rtl?

Thank you.

Tags (1)
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Scholar
Scholar
1,114 Views
Registered: ‎08-07-2014

@fpgatr,

But i have no iade hown can i use bot of them? how to connect blocks? I want to take the stream from the computer and give it to the monitor.  Can i use these ip without processing system, only rtl?

I did it for the Zybo Z7 board. https://github.com/dpaul24/hdmi_pass_through_ZyboZ7-10

You can just adapt it for the Arty. The IP connections should be the same in principle.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer solved your problem.
-------------------------------------------------------------------------------------------------------

View solution in original post

5 Replies
Highlighted
Teacher
Teacher
1,186 Views
Registered: ‎06-16-2013

Hi @fpgatr

 

What problem do you have ?

It is easy way to build this demo with the following README.md file.

 

https://github.com/Digilent/Arty-Z7-10-hdmi-in

https://github.com/Digilent/Arty-Z7-20-hdmi-in

 

Would you refer Demo Setup in README.md ?

 

Best regards,

0 Kudos
Highlighted
Contributor
Contributor
1,135 Views
Registered: ‎07-26-2018

Hi I have a new problem. I try to hdmi pass-throug. From my laptop to monitor. Bu I got an warning massage. It didn't work. I hope someone can help mi. Also I am using pynq z2 and all pins same with arty z7 -20.

 

newerror.JPG

block.JPGclk.JPGclk2.JPGclk3.JPGclk4.JPGclkport.JPGdvitorgb.JPG
rgb2dvi.JPG

 

## This file is a general .xdc for the ARTY Z7-20 Rev.B
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

## Clock Signal

set_property -dict { PACKAGE_PIN H16    IOSTANDARD LVCMOS33 } [get_ports { sys_clock }]; #IO_L13P_T2_MRCC_35 Sch=SYSCLK
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sys_clock }]; 

##Buttons
set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVCMOS33 } [get_ports { rst }]; #IO_L4P_T0_35 Sch=btn[0]


##HDMI RX Signals

#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L13N_T2_MRCC_35 Sch=HDMI_RX_CEC
set_property -dict { PACKAGE_PIN P19   IOSTANDARD TMDS_33  } [get_ports { TMDS_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=HDMI_RX_CLK_N
set_property -dict { PACKAGE_PIN N18   IOSTANDARD TMDS_33  } [get_ports { TMDS_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=HDMI_RX_CLK_P
set_property -dict { PACKAGE_PIN W20   IOSTANDARD TMDS_33  } [get_ports { TMDS_data_n[0]}]; #IO_L16N_T2_34 Sch=HDMI_RX_D0_N
set_property -dict { PACKAGE_PIN V20   IOSTANDARD TMDS_33  } [get_ports { TMDS_data_p[0]}]; #IO_L16P_T2_34 Sch=HDMI_RX_D0_P
set_property -dict { PACKAGE_PIN U20   IOSTANDARD TMDS_33  } [get_ports { TMDS_data_n[1]}]; #IO_L15N_T2_DQS_34 Sch=HDMI_RX_D1_N
set_property -dict { PACKAGE_PIN T20   IOSTANDARD TMDS_33  } [get_ports { TMDS_data_p[1]}]; #IO_L15P_T2_DQS_34 Sch=HDMI_RX_D1_P
set_property -dict { PACKAGE_PIN P20   IOSTANDARD TMDS_33  } [get_ports { TMDS_data_n[2]}]; #IO_L14N_T2_SRCC_34 Sch=HDMI_RX_D2_N
set_property -dict { PACKAGE_PIN N20   IOSTANDARD TMDS_33  } [get_ports { TMDS_data_p[2]}]; #IO_L14P_T2_SRCC_34 Sch=HDMI_RX_D2_P
set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_hpd}]; #IO_25_34 Sch=HDMI_RX_HPD
set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { DDC_scl_io }]; #IO_L11P_T1_SRCC_34 Sch=HDMI_RX_SCL
set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { DDC_sda_io }]; #IO_L11N_T1_SRCC_34 Sch=HDMI_RX_SDA

##HDMI TX Signals

#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L19N_T3_VREF_35 Sch=HDMI_TX_CEC
set_property -dict { PACKAGE_PIN L17   IOSTANDARD TMDS_33  } [get_ports { TMDS_1_clk_n }]; #IO_L11N_T1_SRCC_35 Sch=HDMI_TX_CLK_N
set_property -dict { PACKAGE_PIN L16   IOSTANDARD TMDS_33  } [get_ports { TMDS_1_clk_p }]; #IO_L11P_T1_SRCC_35 Sch=HDMI_TX_CLK_P
set_property -dict { PACKAGE_PIN K18   IOSTANDARD TMDS_33  } [get_ports { TMDS_1_data_n[0] }]; #IO_L12N_T1_MRCC_35 Sch=HDMI_TX_D0_N
set_property -dict { PACKAGE_PIN K17   IOSTANDARD TMDS_33  } [get_ports { TMDS_1_data_p[0]  }]; #IO_L12P_T1_MRCC_35 Sch=HDMI_TX_D0_P
set_property -dict { PACKAGE_PIN J19   IOSTANDARD TMDS_33  } [get_ports { TMDS_1_data_n[1]  }]; #IO_L10N_T1_AD11N_35 Sch=HDMI_TX_D1_N
set_property -dict { PACKAGE_PIN K19   IOSTANDARD TMDS_33  } [get_ports { TMDS_1_data_p[1]  }]; #IO_L10P_T1_AD11P_35 Sch=HDMI_TX_D1_P
set_property -dict { PACKAGE_PIN H18   IOSTANDARD TMDS_33  } [get_ports { TMDS_1_data_n[2]  }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=HDMI_TX_D2_N
set_property -dict { PACKAGE_PIN J18   IOSTANDARD TMDS_33  } [get_ports { TMDS_1_data_p[2]  }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=HDMI_TX_D2_P
 

0 Kudos
Highlighted
Moderator
Moderator
1,120 Views
Registered: ‎11-09-2015

Hi @fpgatr,

The warning message you are getting is related to ILA. Did you add any ILA in your design? I do not see it in your block design.

WIth that said, it would be the good option for debugging to add an ILA and see if you are getting any data from the hdmi in first.

If you want to do step by step, you can start by doing only HDMI out. You might want to look at my video series 23 for an example on pynq-z2

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Highlighted
Scholar
Scholar
1,115 Views
Registered: ‎08-07-2014

@fpgatr,

But i have no iade hown can i use bot of them? how to connect blocks? I want to take the stream from the computer and give it to the monitor.  Can i use these ip without processing system, only rtl?

I did it for the Zybo Z7 board. https://github.com/dpaul24/hdmi_pass_through_ZyboZ7-10

You can just adapt it for the Arty. The IP connections should be the same in principle.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer solved your problem.
-------------------------------------------------------------------------------------------------------

View solution in original post

Highlighted
Moderator
Moderator
1,072 Views
Registered: ‎11-09-2015

HI @fpgatr ,

Do you have any updaes on this? Is your issue solved?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos