04-08-2020 02:26 AM
Hi,
I'm trying to make working the hdmi tx susbsystem with petalinux, I solved some errors, but now I get this:
[ 6.830784] xilinx-vphy a0010000.vid_phy_controller: probed [ 6.836910] VPhy version : 02.02 (0000) [ 6.841292] xilinx-vphy a0010000.vid_phy_controller: probe successful [ 6.865871] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: probed [ 6.871158] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: hdmi tx audio disabled in DT [ 6.878328] xvphy_phy_init((____ptrval____)). [ 6.882706] xvphy_phy_init((____ptrval____)). [ 6.887074] xvphy_phy_init((____ptrval____)). [ 6.891458] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: tx-clk not ready -EPROBE_DEFER
This is my system-user, I modified the file following some indications that I found in other posts on the forum.
&amba_pl{ refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; si5324: clock-generator@68 { status = "okay"; compatible = "silabs,si5324"; reg = <68>; #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clk0 { reg = <0>; clock-frequency = <27000000>; }; }; dp159: hdmi-retimer@5e { status = "okay"; compatible = "ti,dp159"; reg = <0x5e>; #address-cell = <1>; #size-cells = <0>; #clock-cells = <0>; }; }; &v_hdmi_tx_ss_0 { clock-names = "s_axi_cpu_aclk", "link_clk", "s_axis_audio_aclk", "video_clk", "s_axis_video_aclk", "txref-clk", "retimer-clk"; clocks = <&misc_clk_0>, <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_3>, <&misc_clk_0>, <&si5324 0>, <&dp159>; phy-names = "hdmi-phy0", "hdmi-phy1", "hdmi-phy2"; phys = <&vphy_lane0 0 1 1 1>, <&vphy_lane1 0 1 1 1>, <&vphy_lane2 0 1 1 1>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; xlnx,video-format = <XVIP_VF_RBG>, <XVIP_VF_YUV_422>, <XVIP_VF_YUV_420>; xlnx,video-width = <8>; hdmi_txss_in: endpoint { remote-endpoint = <&tpg_out>; }; }; }; };
Andrea
04-23-2020 07:57 PM
Hi andrea@ross ,
Can you share some more details.
04-23-2020 11:43 PM
Hi @sandeepg ,
I'm using petalinux 2019.1 and this is my pl.dtsi file
/ { amba_pl: amba_pl@0 { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; ranges ; axi_iic_0: i2c@a0002000 { #address-cells = <1>; #size-cells = <0>; clock-names = "s_axi_aclk"; clocks = <&misc_clk_0>; compatible = "xlnx,axi-iic-2.0", "xlnx,xps-iic-2.00.a"; reg = <0x0 0xa0002000 0x0 0x1000>; }; misc_clk_0: misc_clk_0 { #clock-cells = <0>; clock-frequency = <147207500>; compatible = "fixed-clock"; }; eth_dma: dma@a0000000 { #dma-cells = <1>; clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; clocks = <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_1>; compatible = "xlnx,eth-dma"; interrupt-names = "mm2s_introut", "s2mm_introut"; interrupt-parent = <&gic>; interrupts = <0 89 4 0 90 4>; reg = <0x0 0xa0000000 0x0 0x1000>; xlnx,include-dre ; }; misc_clk_1: misc_clk_1 { #clock-cells = <0>; clock-frequency = <156250000>; compatible = "fixed-clock"; }; psu_ctrl_ipi: PERIPHERAL@ff380000 { compatible = "xlnx,PERIPHERAL-1.0"; reg = <0x0 0xff380000 0x0 0x80000>; }; psu_message_buffers: PERIPHERAL@ff990000 { compatible = "xlnx,PERIPHERAL-1.0"; reg = <0x0 0xff990000 0x0 0x10000>; }; v_hdmi_tx_ss_0: v_hdmi_tx_ss@a0020000 { clock-names = "s_axi_cpu_aclk", "link_clk", "s_axis_audio_aclk", "video_clk", "s_axis_video_aclk"; clocks = <&misc_clk_0>, <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_3>, <&misc_clk_0>; compatible = "xlnx,v-hdmi-tx-ss-3.1", "xlnx,v-hdmi-tx-ss-3.1"; interrupt-names = "irq"; interrupt-parent = <&gic>; interrupts = <0 91 4>; reg = <0x0 0xa0020000 0x0 0x20000>; xlnx,input-pixels-per-clock = <4>; xlnx,max-bits-per-component = <8>; }; misc_clk_2: misc_clk_2 { #clock-cells = <0>; clock-frequency = <148500000>; compatible = "fixed-clock"; }; misc_clk_3: misc_clk_3 { #clock-cells = <0>; clock-frequency = <297000000>; compatible = "fixed-clock"; }; v_tpg: v_tpg@a0040000 { clock-names = "ap_clk"; clocks = <&misc_clk_0>; compatible = "xlnx,v-tpg-8.0", "xlnx,v-tpg-7.0"; reg = <0x0 0xa0040000 0x0 0x10000>; xlnx,max-height = <2160>; xlnx,max-width = <3840>; xlnx,ppc = <4>; xlnx,s-axi-ctrl-addr-width = <8>; xlnx,s-axi-ctrl-data-width = <32>; }; vid_phy_controller_0: vid_phy_controller@a0010000 { clock-names = "mgtrefclk0_pad_p_in", "mgtrefclk0_pad_n_in", "vid_phy_tx_axi4s_aclk", "vid_phy_sb_aclk", "vid_phy_axi4lite_aclk", "drpclk"; clocks = <&misc_clk_4>, <&misc_clk_4>, <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>; compatible = "xlnx,vid-phy-controller-2.2", "xlnx,vid-phy-controller-2.1"; interrupt-names = "irq"; interrupt-parent = <&gic>; interrupts = <0 92 4>; reg = <0x0 0xa0010000 0x0 0x10000>; xlnx,hdmi-fast-switch = <1>; xlnx,input-pixels-per-clock = <4>; xlnx,nidru = <0>; xlnx,nidru-refclk-sel = <0>; xlnx,rx-no-of-channels = <3>; xlnx,rx-pll-selection = <0>; xlnx,rx-protocol = <3>; xlnx,rx-refclk-sel = <0>; xlnx,transceiver-type = <5>; xlnx,transceiver-width = <4>; xlnx,tx-buffer-bypass = <1>; xlnx,tx-no-of-channels = <3>; xlnx,tx-pll-selection = <6>; xlnx,tx-protocol = <1>; xlnx,tx-refclk-sel = <0>; vphy_lane0: vphy_lane@0 { #phy-cells = <4>; }; vphy_lane1: vphy_lane@1 { #phy-cells = <4>; }; vphy_lane2: vphy_lane@2 { #phy-cells = <4>; }; vphy_lane3: vphy_lane@3 { #phy-cells = <4>; }; }; misc_clk_4: misc_clk_4 { #clock-cells = <0>; clock-frequency = <100000000>; compatible = "fixed-clock"; }; xxv_ethernet_0: ethernet@a0001000 { axistream-connected = <ð_dma>; axistream-control-connected = <ð_dma>; clock-frequency = <100000000>; clock-names = "rx_core_clk_0", "dclk", "gt_refclk_p", "gt_refclk_n", "s_axi_aclk_0"; clocks = <&misc_clk_1>, <&misc_clk_5>, <&misc_clk_4>, <&misc_clk_4>, <&misc_clk_0>; compatible = "xlnx,xxv-ethernet-3.0", "xlnx,xxv-ethernet-1.0"; device_type = "network"; local-mac-address = [00 0a 35 00 00 01]; phy-mode = "base-r"; reg = <0x0 0xa0001000 0x0 0x1000>; xlnx = <0x0>; xlnx,add-gt-cntrl-sts-ports = <0x0>; xlnx,anlt-clk-in-mhz = <0x64>; xlnx,axis-tdata-width = <0x40>; xlnx,axis-tkeep-width = <0x7>; xlnx,base-r-kr = "BASE-R"; xlnx,clocking = "Asynchronous"; xlnx,core = "Ethernet MAC+PCS/PMA 64-bit"; xlnx,data-path-interface = "AXI Stream"; xlnx,enable-datapath-parity = <0x0>; xlnx,enable-pipeline-reg = <0x0>; xlnx,enable-preemption = <0x0>; xlnx,enable-preemption-fifo = <0x0>; xlnx,enable-rx-flow-control-logic = <0x0>; xlnx,enable-time-stamping = <0x0>; xlnx,enable-tx-flow-control-logic = <0x0>; xlnx,enable-vlane-adjust-mode = <0x0>; xlnx,family-chk = "zynquplus"; xlnx,fast-sim-mode = <0x0>; xlnx,gt-diffctrl-width = <0x4>; xlnx,gt-drp-clk = "100.00"; xlnx,gt-group-select = "Quad X0Y0"; xlnx,gt-location = <0x1>; xlnx,gt-ref-clk-freq = "156.25"; xlnx,gt-type = "GTH"; xlnx,include-auto-neg-lt-logic = "None"; xlnx,include-axi4-interface = <0x1>; xlnx,include-dre ; xlnx,include-fec-logic = <0x0>; xlnx,include-hybrid-cmac-rsfec-logic = <0x0>; xlnx,include-rsfec-logic = <0x0>; xlnx,include-shared-logic = <0x1>; xlnx,include-statistics-counters = <0x1>; xlnx,include-user-fifo = <0x1>; xlnx,ins-loss-nyq = <0xa>; xlnx,lane1-gt-loc = "X0Y10"; xlnx,lane2-gt-loc = "NA"; xlnx,lane3-gt-loc = "NA"; xlnx,lane4-gt-loc = "NA"; xlnx,line-rate = <0xa>; xlnx,mii-ctrl-width = <0x4>; xlnx,mii-data-width = <0x20>; xlnx,num-of-cores = <0x1>; xlnx,ptp-clocking-mode = <0x0>; xlnx,ptp-operation-mode = <0x2>; xlnx,runtime-switch = <0x0>; xlnx,rx-eq-mode = "AUTO"; xlnx,rxmem = <0x40000>; xlnx,statistics-regs-type = <0x0>; xlnx,switch-1-10-25g = <0x0>; xlnx,tx-latency-adjust = <0x0>; xlnx,tx-total-bytes-width = <0x4>; xlnx,xgmii-interface = <0x1>; xxv_ethernet_0_mdio: mdio { #address-cells = <1>; #size-cells = <0>; }; }; misc_clk_5: misc_clk_5 { #clock-cells = <0>; clock-frequency = <99990000>; compatible = "fixed-clock"; }; }; };
Thanks, Andrea
04-27-2020 02:33 PM
Hi andrea@ross ,
From your pl.dtsi I don't see any DMA IP associated with HDMI Tx. In order to probe HDMI Tx driver you need Framebuffer Read IP.
DDR -> Framebuf Rd -> HDMI Tx
Once you fix your vivado design then you can post the latest pl.dtsi.