how to debug while hdmi_tx_ss is unlocked ?

[tom.ymwang]

i think you have give an good "how to debug" example for video_in_stream_out ,

and could you please give a example for "how to debug" of hdmi_tx_ss unlocked issue ?

[watari]

Hi @tom.ymwang

I suggest to read @florentw 's Xilinx Video Series.

https://forums.xilinx.com/t5/Video/Xilinx-Video-Series/td-p/849583

There are a lot of tips and helpful explanation for beginner.

Also, I suggest to make sure status signal on axi4stream to video out.

Best regards,

[florentw]

Hi @tom.ymwang,

For the moment I didn't write any Video Series for how to debug the HDMI SS IP.

The best resource for this is the Debugging section of the PG235. Make sure you followed all the recommendations.

Best Regards,

[tom.ymwang]

it seems every thing are OK , but hdmi_tx_ss is unlocked 

VPHY log
------
TX frequency event
TX timer event
TX MMCM reconfig done
QPLL reconfig done
GT TX reconfig start
GT TX reconfig done
QPLL lock
TX reset done
TX alignment done
TX frequency event
QPLL lost lock
TX frequency event
TX timer event
TX MMCM reconfig done
QPLL reconfig done
GT TX reconfig start
GT TX reconfig done
QPLL lock
TX reset done
TX alignment done
TX frequency event
QPLL lost lock
TX frequency event
TX timer event
TX MMCM reconfig done
QPLL reconfig done
GT TX reconfig start
GT TX reconfig done
QPLL lock
TX reset done
TX alignment done

HDMI TX log
------
TX Stream is Up
TX Stream is Down
TX Stream is Up
TX Stream is Down
TX Stream is Up

[samk]

Hi @tom.ymwang,

Can you tell us how you are checking locked?

Locked refers to the input stream into the HDMI TX core and not the output stream. 

Locked high:

The video frames into the HDMI core are being "locked".

Locked low:

The HDMI TX Subsystem has not yet been able to lock onto the incoming video frames.

Please see PG235 for more information.

Regards,

Sam

[tom.ymwang]

i used the "VIO" 

[watari]

Hi @tom.ymwang

I suggest to make sure status signal on "axi4stream to video output IP" if you use.

Also, would you share us this value and your block diagram ?

It points out the route cause of this issue.

Best regards,

[tom.ymwang]

seems something wrong , the status are 0x000c0387

i used 74.25 for 2 pixel per clock ,

and the VTC configuration is as following ,

can you explain more detail for me ?  thanks 

[tom.ymwang]

the block diagram as the following , and red line path is work well ,

[tom.ymwang]

[samk]

Hi @tom.ymwang,

To summarize what we know.

1. Using the VTPG to the data fifo to register slice to HDMI TX everything works correctly.

2. You are using 2 PPC mode with a 74.24 clock.

3. Based on your VTC configuration your resolution is 960x1080

4. When you add in a VTC +AXI4-Stream to Video Out +Video Into AXI4-Stream, your HDMI no longer locks to the incoming video.

Moving forward:

1. In your configuration without the Video in and Video out cores, is working are you using a 960x1080 resolution?

2. Please take a look at the video series showing an example of what you are doing.

       https://forums.xilinx.com/t5/Video/Video-Beginner-Series-6-From-AXI4-Stream-to-Native-Video/td-p/862633

       https://forums.xilinx.com/t5/Video/Video-Beginner-Series-2-From-Native-video-to-AXI4-Stream/td-p/851073

3. Once you have looked at the video series. If you still have issues, break this problem up into steps.

Step 1. Is the resolution 960x1080 into the AXI4-Stream to Video Out correct? If so move to step 2.

Step 2. Is the output from the AXI4-Stream to Video Out correct? If so move to step 3. If not, verify your settings and check the statuses of the VTC and AXI4-Stream to Video Out cores.

Step 3. Is the output from the Video In to AXI4-Stream correct? If so move to step 4. If not, verify your settings and check the status of the Video In to AXI4-Stream core.

Step 4. Re-check the locked signal. At this point, the locked signal should lock.

**To verify if the streams are correct, you can use the debug logs through the processor and/or add ILAs into your design to inspect the streams by hand.

Regards,

Sam

[tom.ymwang]

thanks , i will follow up your steps ,

and may i have a question :

actually , i wanted to display 1080P X60 to hdmi ,please check the following setting 

(1) TPG setting 2 ppc , RGB 888 

(2) VTC setting 960x1080 (???) for 2 PPC

(3) and other  IPs setting 2 ppc

(4) clock tree : 100M -> clk_1485(148.5MHz) to external PLL and feed back to mgtref_clk_p/n , and clk_1485 /2 to  clk_7425 to tpg,vtc,hdmi's s_axis_video_aclk and others buffer .

have something wrong ?

[samk]

1. If your TPG is set to 888, your other IP will need to be set to 888. This is done through the drivers (firmware)

2. The screenshot of your VTC is listed at 960x1080. This should be 1920x1080

3. all Ip in the video pipe should be set at the same PPC.

4. Your VTC, TPG and all other AXIS cores are not directly tied to the link clock speed. They can be any speed, and the requirement is that they are fast enough to transfer all of the data. I believe that 74.25 should be fine, but you can verify this by checking for underflow in your cores to verify that your AXI-Stream is running fast enough. Take a look at http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf for more information on AXIS + Video. 

-Sam

[florentw]

Hi @tom.ymwang,

Do you have any updates on this? Were the replies from @samk enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,