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Observer
Observer
11,870 Views
Registered: ‎11-14-2013

image enhancement v8.0 issues

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Hello,

 

I am using xilinx image enhancement v8.0 in my porjects. Everything is OK except setting register 0x0020 via AXI interface.

The register is needed to be set when input video resolution changed. It seems the active h size value can't be set.

I found xilinx has a solution about this issues(AR# 60173):

Why does the Image Enhancement core output data in the wrong columns after changing the number of columns via the AXI4-Lite interface?

This is a known issue with the Image Enhancement core v8.0 (Rev. 1), v8.0 (Rev. 2), v8.0 (Rev. 3).

The user can work around this issue by asserting the sclr input pin after changing the columns.

This issue will be resolved in a future release of the Image Enhancement core.

 

 

My question is where "the sclr input pin" is ?

Can I have a work around solution ?

 

 

Thanks,

 

Kim

 

 

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Observer
Observer
15,437 Views
Registered: ‎11-14-2013

Hi All,

 

This bug is fixed in new Vivado2014.2 Release.

 

 

Kim

 

 

 

View solution in original post

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11 Replies
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Xilinx Employee
Xilinx Employee
11,863 Views
Registered: ‎08-02-2011
Hi Kim,

I believe that should be 'aresetn' not 'sclr'
www.xilinx.com
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Observer
Observer
11,831 Views
Registered: ‎11-14-2013

Hi bwiec,

 

I tried to pull "aresetn" low for 16ms after setting Reg 0x0020. The video totally lost.

Can I have a detail timing description ?

 

Thanks,

 

Kim

 

 

 

 

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Contributor
Contributor
11,790 Views
Registered: ‎08-09-2013

I think I have the same issue here.

 

I use the Enhance 8.0 core to run a 1-shot image processing.

I input say 256 lines of say 256 pixels with the same "counting value" (0 to 255).

The input of the CORE is correct (successive lines with TLAST asserted and same value for the entire line).

The output of the CORE actually pushes out the last 16 lines (i.e: 240, 241, etc...) ahead of the new lines, resulting in an image shift.

 

I suspect that this might be because I am using the AXI Lite port to configure the ACTIVE_SIZE register.

 

I also do not know what is meant by sclr. Doing a soft reset (via CONTROL register) or a hard reset, or disable, all result in the Core loosing its configuration.

 

Any help or a fix will be welcome.

Thanks

 

 

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Contributor
Contributor
11,776 Views
Registered: ‎08-09-2013

hi bwiec,

Can you please help clarify which aresetn you are talking about?

Should it be S_AXI_ARESETn of the AXI Lite configuration interface, or the ARESETn input reset signal?

 

I think doing a ARESETn just resets all programmed values to default so I don't think that is the solution?

 

There is definitely an error with the enhance core whenever changing HSIZE to a value that's not the default Core value.

 

Some guidance on this will be greatly appreciated,

thanks!

 

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Contributor
Contributor
11,766 Views
Registered: ‎08-09-2013

Hello... me again.

The fix proposed doesn't work. Asserting ARESET_N will reset the core (hence lose the ACTIVE_SIZE info), and reprogramming the line size with a value different from the default will always result in odd filtering results.

 

It will be great if that gets resolved soon,

Thanks

 

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Observer
Observer
11,695 Views
Registered: ‎11-14-2013

Can anybody answer the question or need to post to other board ?

Please!

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Xilinx Employee
Xilinx Employee
11,692 Views
Registered: ‎08-01-2007

You might want to try delaying the reset until after the TUSER_SOF following the update to the registers.  This is because the registers are double buffered and do not actually take affect until after an TUSER_SOF.

Chris
Versal ACAP: AI Engines | Embedded SW Support

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Observer
Observer
11,634 Views
Registered: ‎11-14-2013

Hi Chris,

 

Thank you for your reply.

I have ever tried to delay reset after or before TUSER_SOF, dosen't work.

 

 

Kim

 

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Xilinx Employee
Xilinx Employee
11,607 Views
Registered: ‎08-02-2011

The core resets have a requirement that they be asserted for 32 clock cycles. Have you done this?

www.xilinx.com
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Observer
Observer
8,476 Views
Registered: ‎11-14-2013

Hi bwiec,

 

Yes, I did.

 

 

Kim

 

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Highlighted
Observer
Observer
15,438 Views
Registered: ‎11-14-2013

Hi All,

 

This bug is fixed in new Vivado2014.2 Release.

 

 

Kim

 

 

 

View solution in original post

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