04-18-2021 07:00 PM
The development environment is vivado: 2019.2, which realizes the function of DVI video input and 3G SDI video output. The current process is such a DVI video input, using the DVI video source clock (148.5mhz) to transmit the clock to the GTX clock 148.5mhz clock source through the PLL. The reason for this is that I don't want to use VDMA to cache the video. If the motherboard 148.5mhz crystal oscillator is used, there will be a problem of cross clock domain. But the problem that this brings is that the probability that the system starts about 1/20 sdi cannot be displayed correctly. Does SDI smpte IP support this application method?
04-19-2021 04:05 AM
Hello @linyipa ,
We recommend to use on board oscillator source for 148.5Mhz clock, which is a source to GTH/GTY/GTX/GTP transceiver. But, your use case seems to be different. you are using a DVI source, instead of SDI source to pump the SDI video to the FPGA.
Are you using any converters to convert the DVI video data to SDI video data? If yes, what is that and can you confirm, does that converter is compliance of SDI standard?
Have you tried to use, our XAPP's? If not, for your reference kindly go through those applications like XAPP592.
the above xapp helps you, to give a basic idea about the clocking and FIFO requirement for a simple pass through application.
Hope the above information is helpful to you.
04-28-2021 12:45 AM
Hi @linyipa ,
Do you have any questions about this thread. If not, please make sure that to mark the post as accepted solution, which was helpful to you. If yes, please give me more inputs to debug about this case.