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systemsdeveloper
Explorer
Explorer
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Registered: ‎06-10-2019

media-ctl doesn't find /dev/media0 and no hdmi rx ss>/hdmi_info, ZCU106 HDMI framebuffer passthrough

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HI All,

I am trying to test hdmi rx functionality as per this :

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841884/Xilinx+V4L2+hdmirx+driver

following test procedure:

media-ctl -p -d /dev/media0

i am getting this error:

root@hdmi_only:~# media-ctl -p -d /dev/media0
Failed to enumerate /dev/media0 (-2)

error make sence as no medio0 in dev.

Next step , i thought lets have look with v4l2-ctl --all

root@hdmi_only:~# v4l2-ctl --all
Driver Info:
Driver name : xilinx-vipp
Card type : vcap_hdmi output 0
Bus info : platform:vcap_hdmi:0
Driver version : 4.19.0
Capabilities : 0x84201000
Video Capture Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04201000
Video Capture Multiplanar
Streaming
Extended Pix Format
Priority: 2
Video input : 0
Format Video Capture Multiplanar:
Width/Height : 1920/0
Pixel Format : 'YUYV'
Field : None
Number of planes : 0
Flags :
Colorspace : sRGB
Transfer Function : Default
YCbCr/HSV Encoding: Default
Quantization : Default
root@hdmi_only:~#

 

root@hdmi_only:~# v4l2-ctl -D
Driver Info:
Driver name : xilinx-vipp
Card type : vcap_hdmi output 0
Bus info : platform:vcap_hdmi:0
Driver version : 4.19.0
Capabilities : 0x84201000
Video Capture Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04201000
Video Capture Multiplanar
Streaming
Extended Pix Format
root@hdmi_only:~#

 

 

Next step was , check any debug info but nothing like hdmi_info:

root@hdmi_only:/sys/devices/platform/amba_pl@0# ls
80000000.v_hdmi_rx_ss     
80020000.v_hdmi_tx_ss       80050000.v_frmbuf_wr          amba_pl@0:drm-dmaengine-drv         driver_override ff990000.PERIPHERAL       of_node subsystem    80010000.v_frmbuf_rd    80041000.i2c 80060000.vid_phy_controller amba_pl@0:vcap_hdmi ff380000.PERIPHERAL modalias power uevent


root@hdmi_only:/sys/devices/platform/amba_pl@0# cd 80000000.v_hdmi_rx_ss/


root@hdmi_only:/sys/devices/platform/amba_pl@0/80000000.v_hdmi_rx_ss# ls

driver_override     modalias of_node     power subsystem uevent

--------------------------------------------------------------

root@hdmi_only# v4l2-ctl --list-devices
vcap_hdmi output 0 (platform:vcap_hdmi:0):
/dev/video0

----------------------------------------------------------------

root@hdmi_only# ls /sys/class/video4linux/video0/device/ | grep -i media

found nothing.....

---------------------------------------------------------------

----------I am not sure what to look next for debugging.

How to check hotplug detection?

hdmi_rx ip set with hot plug detect active -> HIGH and cable detect active ->low.

I am using zcu106 fpga.

 

Any ideas to solve this problem?

Thanks in advance.

Note: i have add  HDMI TX  IP block for future testing.

 

demsg log related to hdmi block:

[ 4.598090] Key type asymmetric registered
[ 4.598129] Asymmetric key parser 'x509' registered
[ 4.601424] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
[ 4.608759] io scheduler noop registered
[ 4.612638] io scheduler deadline registered
[ 4.616910] io scheduler cfq registered (default)
[ 4.621548] io scheduler mq-deadline registered
[ 4.626045] io scheduler kyber registered
[ 4.631568] xilinx-frmbuf 80010000.v_frmbuf_rd: failed to get ap_clk (-517)
[ 4.636982] xilinx-frmbuf 80050000.v_frmbuf_wr: failed to get ap_clk (-517)
[ 4.670129] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 4.673920] xlnx-pl-disp amba_pl@0:drm-dmaengine-drv: failed to request dma channel
[ 4.678681] cacheinfo: Unable to detect cache hierarchy for CPU 0
[ 4.689039] brd: module loaded
[ 4.692907] loop: module loaded

 

[ 5.162781] of-fpga-region fpga-full: FPGA Region probed
[ 5.171464] xilinx-zynqmp-dma fd500000.dma: ZynqMP DMA driver Probe success
[ 5.178573] xilinx-zynqmp-dma fd510000.dma: ZynqMP DMA driver Probe success
[ 5.185680] xilinx-zynqmp-dma fd520000.dma: ZynqMP DMA driver Probe success
[ 5.192776] xilinx-zynqmp-dma fd530000.dma: ZynqMP DMA driver Probe success
[ 5.199884] xilinx-zynqmp-dma fd540000.dma: ZynqMP DMA driver Probe success
[ 5.206990] xilinx-zynqmp-dma fd550000.dma: ZynqMP DMA driver Probe success
[ 5.214092] xilinx-zynqmp-dma fd560000.dma: ZynqMP DMA driver Probe success
[ 5.221188] xilinx-zynqmp-dma fd570000.dma: ZynqMP DMA driver Probe success
[ 5.228370] xilinx-zynqmp-dma ffa80000.dma: ZynqMP DMA driver Probe success
[ 5.235474] xilinx-zynqmp-dma ffa90000.dma: ZynqMP DMA driver Probe success
[ 5.242572] xilinx-zynqmp-dma ffaa0000.dma: ZynqMP DMA driver Probe success
[ 5.249673] xilinx-zynqmp-dma ffab0000.dma: ZynqMP DMA driver Probe success
[ 5.256772] xilinx-zynqmp-dma ffac0000.dma: ZynqMP DMA driver Probe success
[ 5.263878] xilinx-zynqmp-dma ffad0000.dma: ZynqMP DMA driver Probe success
[ 5.270973] xilinx-zynqmp-dma ffae0000.dma: ZynqMP DMA driver Probe success
[ 5.278081] xilinx-zynqmp-dma ffaf0000.dma: ZynqMP DMA driver Probe success
[ 5.285181] xilinx-frmbuf 80010000.v_frmbuf_rd: Xilinx AXI frmbuf DMA_MEM_TO_DEV
[ 5.292628] xilinx-frmbuf 80010000.v_frmbuf_rd: Xilinx AXI FrameBuffer Engine Driver Probed!!
[ 5.301267] xilinx-frmbuf 80050000.v_frmbuf_wr: Xilinx AXI frmbuf DMA_DEV_TO_MEM
[ 5.308724] xilinx-frmbuf 80050000.v_frmbuf_wr: Xilinx AXI FrameBuffer Engine Driver Probed!!
[ 5.317377] xlnx-pl-disp amba_pl@0:drm-dmaengine-drv: vtc bridge property not present
[ 5.325302] xlnx-pl-disp amba_pl@0:drm-dmaengine-drv: Xlnx PL display driver probed
[ 5.333939] m25p80 spi0.0: n25q512a (131072 Kbytes)
[ 5.338830] 3 fixed-partitions partitions found on MTD device spi0.0
[ 5.345172] Creating 3 MTD partitions on "spi0.0":
[ 5.349957] 0x000000000000-0x000000100000 : "boot"
[ 5.355149] zynqmp_pll_disable() clock disable failed for apll_int, ret = -13
[ 5.362436] 0x000000100000-0x000000140000 : "bootenv"
[ 5.367896] 0x000000140000-0x000001740000 : "kernel"
[ 5.375268] macb ff0e0000.ethernet: Not enabling partial store and forward

 

----------I am using 2019.1 version.

hdmi_rx0.PNG
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1 Solution

Accepted Solutions
kvasantr
Moderator
Moderator
3,632 Views
Registered: ‎04-12-2017

Hello @systemsdeveloper 

Apologies for late reply on this. Allow me to answer two of your questions that you asked in your previous post:

(1) Why my auto-generated pl.dts file doesnt cover si570_2 & dru-clk information even when i have connected dru-clk select in IP configuration?

- We have this know issue with our DTG tool and we have an answer record that. you will need to make a manual device tree entry from system-user.dtsi to add this clocks. please refer following https://www.xilinx.com/support/answers/72454.html. Also we have this ready device tree entries available with our VCU TRD package in following path. W:\rdf0428-zcu106-vcu-trd-2019-2\apu\xilinx-vcu-zcu106-v2019.2-final\project-spec\meta-user\recipes-bsp\device-tree\files

we have steps to use those files in following wiki link.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/176914576/Zynq+UltraScale+MPSoC+VCU+TRD+2019.2+-+Run+and+Build+Flow

(2) How can I stop petalinux build to clean up HDMI source code after build? (I am adding  IMAGE_INSTALL_append = " kernel-module-hdmi" in meta-user/recipes-core/images/petalinux-image-full.bbappend) I would like to modify source code internally and want my build to use local checkout hdmi source code. 

Any ideas to solve this problem?

please use IMAGE_INTALL_remove instead of append. that should help resolve this query.

Regards

Kunal

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29 Replies
watari
Teacher
Teacher
4,321 Views
Registered: ‎06-16-2013

Hi @systemsdeveloper 

 

Would you share whole boot log file ?

 

Best regards,

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samk
Moderator
Moderator
4,261 Views
Registered: ‎10-04-2017

Hi @systemsdeveloper,

Are you still running into an issue?
If so, please share your log with the community so that we can help.

If not, do you mind sharing how you fixed the issue to help the community in the future?


Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
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kvasantr
Moderator
Moderator
4,238 Views
Registered: ‎04-12-2017

Hello @systemsdeveloper 

Can we also look into your generated device tree and video block design in the PL?

That would help if that's one reason of video device created or not.

Regards

Kunal

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systemsdeveloper
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Registered: ‎06-10-2019

@samk 

@watari   

@kvasantr 

Some reason, my last reply  sent successfully but not appared on this reply thread, so re-writing again:

HDMI failing log:

[ 6.426167] xilinx_vphy: loading out-of-tree module taints kernel.
[ 6.427422] xilinx_vphy: loading out-of-tree module taints kernel.
[ 6.451389] xilinx-vphy 80060000.vid_phy_controller: probed
[ 6.459754] xilinx-vphy 80060000.vid_phy_controller: failed to get the nidru clk.
[ 6.467501] xilinx-vphy: probe of 80060000.vid_phy_controller failed with error -2
[ 6.482014] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: probed
[ 6.490885] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: probed
[ 6.496199] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: hdmi tx audio disabled in DT
[ 6.503378] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: xvphy not ready -EPROBE_DEFER
[ 6.512194] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: xvphy not ready -EPROBE_DEFER

 

 yes, its dts realated issue. Auto-generated PL.dts file doesnt contain information related to nidru clk.

phy-vphy.c file throwing this error "vid_phy_controller: failed to get the nidru clk" as doesnt find "nidru clk" clk information.

v_hdmi_tx_ss: v_hdmi_tx_ss@80020000 {
clock-names = "s_axi_cpu_aclk", "link_clk", "s_axis_audio_aclk", "video_clk", "s_axis_video_aclk";
clocks = <&zynqmp_clk 74>, <&misc_clk_0>, <&zynqmp_clk 74>, <&misc_clk_1>, <&zynqmp_clk 72>;
compatible = "xlnx,v-hdmi-tx-ss-3.1", "xlnx,v-hdmi-tx-ss-3.1";
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 91 4>;
phy-names = "hdmi-phy0", "hdmi-phy1", "hdmi-phy2";
phys = <&vphy_lane0 0 1 1 1>, <&vphy_lane1 0 1 1 1>, <&vphy_lane2 0 1 1 1>;
reg = <0x0 0x80020000 0x0 0x20000>;
xlnx,input-pixels-per-clock = <2>;
xlnx,max-bits-per-component = <8>;
hdmitx_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
encoder_hdmi_port: port@0 {
reg = <0>;
hdmi_encoder: endpoint {
remote-endpoint = <&dmaengine_crtc>;
};
};
};
};
vid_phy_controller: vid_phy_controller@80060000 {
clock-names = "mgtrefclk0_pad_p_in", "mgtrefclk0_pad_n_in", "mgtrefclk1_pad_p_in", "mgtrefclk1_pad_n_in", "gtsouthrefclk0_in", "gtsouthrefclk0_odiv2_in", "vid_phy_tx_axi4s_aclk", "vid_phy_rx_axi4s_aclk", "vid_phy_sb_aclk", "vid_phy_axi4lite_aclk", "drpclk";
clocks = <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_3>, <&misc_clk_3>, <&misc_clk_0>, <&misc_clk_0>, <&zynqmp_clk 74>, <&zynqmp_clk 74>, <&zynqmp_clk 74>;
compatible = "xlnx,vid-phy-controller-2.2", "xlnx,vid-phy-controller-2.1";
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 89 4>;
reg = <0x0 0x80060000 0x0 0x10000>;
xlnx,hdmi-fast-switch = <1>;
xlnx,input-pixels-per-clock = <2>;
xlnx,nidru = <1>;
xlnx,nidru-refclk-sel = <4>;
xlnx,rx-no-of-channels = <3>;
xlnx,rx-pll-selection = <0>;
xlnx,rx-protocol = <1>;
xlnx,rx-refclk-sel = <1>;
xlnx,transceiver-type = <5>;
xlnx,transceiver-width = <2>;
xlnx,tx-buffer-bypass = <1>;
xlnx,tx-no-of-channels = <3>;
xlnx,tx-pll-selection = <6>;
xlnx,tx-protocol = <1>;
xlnx,tx-refclk-sel = <0>;
vphy_lane0: vphy_lane@0 {
#phy-cells = <4>;
};
vphy_lane1: vphy_lane@1 {
#phy-cells = <4>;
};
vphy_lane2: vphy_lane@2 {
#phy-cells = <4>;
};
vphy_lane3: vphy_lane@3 {
#phy-cells = <4>;
};
};
misc_clk_2: misc_clk_2 {
#clock-cells = <0>;
clock-frequency = <100000000>;
compatible = "fixed-clock";
};
misc_clk_3: misc_clk_3 {
#clock-cells = <0>;
clock-frequency = <156250000>;
compatible = "fixed-clock";
};
zynq_us_ss_0_fmch_axi_iic: i2c@80041000 {
#address-cells = <1>;
#size-cells = <0>;
clock-names = "s_axi_aclk";
clocks = <&zynqmp_clk 74>;
compatible = "xlnx,axi-iic-2.0", "xlnx,xps-iic-2.00.a";
interrupt-names = "iic2intc_irpt";
interrupt-parent = <&gic>;
interrupts = <0 94 4>;
reg = <0x0 0x80041000 0x0 0x1000>;
};
vcap_hdmi {
compatible = "xlnx,video";
dma-names = "port0";
dmas = <&v_frmbuf_wr_0 0>;
vcap_hdmi_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
vcap_hdmi_port: port@0 {
direction = "input";
reg = <0>;
vcap_hdmi_in: endpoint {
remote-endpoint = <&hdmi_rx_out>;
};
};
};
};
v_drm_dmaengine_drv: drm-dmaengine-drv {
#address-cells = <1>;
#size-cells = <0>;
/* Fill the fields xlnx,vformat based on user requirement */
compatible = "xlnx,pl-disp";
dma-names = "dma0";
dmas = <&v_frmbuf_rd_0 0>;
xlnx,vformat = "YUYV";
dmaengine_port: port@0 {
reg = <0>;
dmaengine_crtc: endpoint {
remote-endpoint = <&hdmi_encoder>;
};
};
};

------------------------------------------------------------

My Auto-generated pl.dts file missing si570_2 & dru-clk information.

My questions is:

(1) Why my auto-generated pl.dts file doesnt cover si570_2 & dru-clk information even when i have connected dru-clk select in IP configuration?

(2) How can I stop petalinux build to clean up HDMI source code after build? (I am adding  IMAGE_INSTALL_append = " kernel-module-hdmi" in meta-user/recipes-core/images/petalinux-image-full.bbappend) I would like to modify source code internally and want my build to use local checkout hdmi source code. 

Any ideas to solve this problem?

ps. sorry for my late reply as I was on holiday.

 

 

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systemsdeveloper
Explorer
Explorer
4,160 Views
Registered: ‎06-10-2019

Some reason, so many time reply sent successfully but not appared on this reply thread, so re-writing again:
HDMI failing log:
[ 6.426167] xilinx_vphy: loading out-of-tree module taints kernel.
[ 6.427422] xilinx_vphy: loading out-of-tree module taints kernel.
[ 6.451389] xilinx-vphy 80060000.vid_phy_controller: probed
[ 6.459754] xilinx-vphy 80060000.vid_phy_controller: failed to get the nidru clk.
[ 6.467501] xilinx-vphy: probe of 80060000.vid_phy_controller failed with error -2
[ 6.482014] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: probed
[ 6.490885] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: probed
[ 6.496199] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: hdmi tx audio disabled in DT
[ 6.503378] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: xvphy not ready -EPROBE_DEFER
[ 6.512194] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: xvphy not ready -EPROBE_DEFER

yes, its dts realated issue. Auto-generated PL.dts file doesnt contain information related to nidru clk.
phy-vphy.c file throwing this error "vid_phy_controller: failed to get the nidru clk" as doesnt find "nidru clk" clk information.
v_hdmi_tx_ss: v_hdmi_tx_ss@80020000 {
clock-names = "s_axi_cpu_aclk", "link_clk", "s_axis_audio_aclk", "video_clk", "s_axis_video_aclk";
clocks = <&zynqmp_clk 74>, <&misc_clk_0>, <&zynqmp_clk 74>, <&misc_clk_1>, <&zynqmp_clk 72>;
compatible = "xlnx,v-hdmi-tx-ss-3.1", "xlnx,v-hdmi-tx-ss-3.1";
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 91 4>;
phy-names = "hdmi-phy0", "hdmi-phy1", "hdmi-phy2";
phys = <&vphy_lane0 0 1 1 1>, <&vphy_lane1 0 1 1 1>, <&vphy_lane2 0 1 1 1>;
reg = <0x0 0x80020000 0x0 0x20000>;
xlnx,input-pixels-per-clock = <2>;
xlnx,max-bits-per-component = <8>;
hdmitx_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
encoder_hdmi_port: port@0 {
reg = <0>;
hdmi_encoder: endpoint {
remote-endpoint = <&dmaengine_crtc>;
};
};
};
};
vid_phy_controller: vid_phy_controller@80060000 {
clock-names = "mgtrefclk0_pad_p_in", "mgtrefclk0_pad_n_in", "mgtrefclk1_pad_p_in", "mgtrefclk1_pad_n_in", "gtsouthrefclk0_in", "gtsouthrefclk0_odiv2_in", "vid_phy_tx_axi4s_aclk", "vid_phy_rx_axi4s_aclk", "vid_phy_sb_aclk", "vid_phy_axi4lite_aclk", "drpclk";
clocks = <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_3>, <&misc_clk_3>, <&misc_clk_0>, <&misc_clk_0>, <&zynqmp_clk 74>, <&zynqmp_clk 74>, <&zynqmp_clk 74>;
compatible = "xlnx,vid-phy-controller-2.2", "xlnx,vid-phy-controller-2.1";
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 89 4>;
reg = <0x0 0x80060000 0x0 0x10000>;
xlnx,hdmi-fast-switch = <1>;
xlnx,input-pixels-per-clock = <2>;
xlnx,nidru = <1>;
xlnx,nidru-refclk-sel = <4>;
xlnx,rx-no-of-channels = <3>;
xlnx,rx-pll-selection = <0>;
xlnx,rx-protocol = <1>;
xlnx,rx-refclk-sel = <1>;
xlnx,transceiver-type = <5>;
xlnx,transceiver-width = <2>;
xlnx,tx-buffer-bypass = <1>;
xlnx,tx-no-of-channels = <3>;
xlnx,tx-pll-selection = <6>;
xlnx,tx-protocol = <1>;
xlnx,tx-refclk-sel = <0>;
vphy_lane0: vphy_lane@0 {
#phy-cells = <4>;
};
vphy_lane1: vphy_lane@1 {
#phy-cells = <4>;
};
vphy_lane2: vphy_lane@2 {
#phy-cells = <4>;
};
vphy_lane3: vphy_lane@3 {
#phy-cells = <4>;
};
};
misc_clk_2: misc_clk_2 {
#clock-cells = <0>;
clock-frequency = <100000000>;
compatible = "fixed-clock";
};
misc_clk_3: misc_clk_3 {
#clock-cells = <0>;
clock-frequency = <156250000>;
compatible = "fixed-clock";
};
zynq_us_ss_0_fmch_axi_iic: i2c@80041000 {
#address-cells = <1>;
#size-cells = <0>;
clock-names = "s_axi_aclk";
clocks = <&zynqmp_clk 74>;
compatible = "xlnx,axi-iic-2.0", "xlnx,xps-iic-2.00.a";
interrupt-names = "iic2intc_irpt";
interrupt-parent = <&gic>;
interrupts = <0 94 4>;
reg = <0x0 0x80041000 0x0 0x1000>;
};
vcap_hdmi {
compatible = "xlnx,video";
dma-names = "port0";
dmas = <&v_frmbuf_wr_0 0>;
vcap_hdmi_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
vcap_hdmi_port: port@0 {
direction = "input";
reg = <0>;
vcap_hdmi_in: endpoint {
remote-endpoint = <&hdmi_rx_out>;
};
};
};
};
v_drm_dmaengine_drv: drm-dmaengine-drv {
#address-cells = <1>;
#size-cells = <0>;
/* Fill the fields xlnx,vformat based on user requirement */
compatible = "xlnx,pl-disp";
dma-names = "dma0";
dmas = <&v_frmbuf_rd_0 0>;
xlnx,vformat = "YUYV";
dmaengine_port: port@0 {
reg = <0>;
dmaengine_crtc: endpoint {
remote-endpoint = <&hdmi_encoder>;
};
};

My Auto-generated pl.dts file missing si570_2 & dru-clk information.
My questions is:
(1) Why my auto-generated pl.dts file doesnt cover si570_2 & dru-clk information even when i have connected dru-clk select in IP configuration?
(2) How can I stop petalinux build to clean up HDMI source code after build? (I am adding IMAGE_INSTALL_append = " kernel-module-hdmi" in meta-user/recipes-core/images/petalinux-image-full.bbappend) I would like to modify source code internally and want my build to use local checkout hdmi source code.
Any ideas to solve this problem?
ps. sorry for my late reply as I was on holiday.

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watari
Teacher
Teacher
4,116 Views
Registered: ‎06-16-2013

Hi @systemsdeveloper 

 

How do you implement HDMI Rx IP ?

Also, would you share the figure of HDMI Rx IP and clock tree on board design ?

You must make sure connection between HDMI Rx IP and clock source and clock tree, too.

 

Best regards,

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systemsdeveloper
Explorer
Explorer
4,072 Views
Registered: ‎06-10-2019

Attached clock tree buffer as much possible and video phy settings. dru-clk is connected to external clock buffer on ZCU106 zynqMP ultrscale. 

clock_buffer_1.PNG
video_phy.PNG
video_phy_settings.PNG
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systemsdeveloper
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Registered: ‎06-10-2019

@watari 

let me know if you need any more information, FYI, if i dont use dru-clk , HDMI RX susbystems driver is happy and it does setup correctly 4K@60 but i really want to use dru-clk for low resolutions.

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once I disable dru-clk, hdmi rx susbsytem looks ok but HDMI TX driver is not happy.... 

[ 5.030767] xilinx_vphy: loading out-of-tree module taints kernel.
[ 5.030770] xilinx_vphy: loading out-of-tree module taints kernel.
[ 5.043850] xilinx-vphy 80060000.vid_phy_controller: probed
[ 5.050030] VPhy version : 02.02 (0000)
[ 5.065612] xilinx-vphy 80060000.vid_phy_controller: probe successful
[ 5.076462] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: probed
[ 5.081754] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: hdmi tx audio disabled in DT
[ 5.088935] xvphy_phy_init((____ptrval____)).
[ 5.093328] xvphy_phy_init((____ptrval____)).
[ 5.093685] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: probed
[ 5.097699] xvphy_phy_init((____ptrval____)).
[ 5.107404] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: failed to get tx-clk.
[ 5.113969] xlnx-drm-hdmi: probe of 80020000.v_hdmi_tx_ss failed with error - 2
[ 5.124088] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: Direct firmware load for xi linx/xilinx-hdmi-rx-edid.bin failed with error -2
[ 5.135540] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: Using Xilinx built-in EDID.
[ 5.142757]
[ 5.142757] Successfully loaded edid.
[ 5.148093] xilinx-video amba_pl@0:vcap_hdmi: Entity type for entity 80000000 .v_hdmi_rx_ss was not initialized!
[ 5.159172] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: probe successful

 

Now, I see wrong with hdmi tx dts, i cant see tx-clk information in dts......is that something ,I am doing wrong? why dts is not correctly generating?

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@watari @kvasantr 

attched HDMI TX IP Settings pic too.

hdmi_tx_settings.PNG
tx_ss.PNG
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watari
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Hi @systemsdeveloper 

 

I found a lot of "input floating" ports in your design.

Would you fix them ?

 

Best regards,

 

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@watari 

I dont see any mendatory floting inputs in design. Floting inputs are for Audio only, I am not using Audio in my application at this moment that's why I left floting. Xilinx Synthesis/routing doesnt throw any error on left audio inputs. By the way, My design is  identical to Xilinx HDMI passthrough reference design, even in xilinx reference design, they left all audio inputs floting. Do you see any critical inputs left floting? or Do we must connect all Audio inputs in all IPs?  

I am refering to this example design:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/142311427/HDMI+FrameBuffer+Example+Design+2019.1 

 

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systemsdeveloper
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I have added Audio connection on all IPs, just for a test, I still dont see pl.dts with dru-clk details. I think, It has nothing to do with left Audio inputs floating/unconnected.

I am seeing two issues in Auto-generated pl.dts by xilinx SW:

(1) dru-clk details doesnt generated in vid_phy_controller, ( pl.dts.)

(2) txref-clk deails doesnt generated in v_hdmi_tx_ss, (pl.dts.)

Logs for (2) issues: All logs  copied in previouse reply

[ 5.107404] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: failed to get tx-clk.
[ 5.113969] xlnx-drm-hdmi: probe of 80020000.v_hdmi_tx_ss failed with error - 2

both this issue throws error on boot time driver loading as explained in previous replies. As I said before, I can disbale dru-clk to get HDMI rx driver happy but I dont know what to do with "txref-clk" which is stopping HDMI TX driver loding correctly. How can i get txref-clk in pl.dts?

I am using 2019.1 version and  using ZCU106 zynqMP

@kvasantr @samk @watari 

Any suggestion on this issues?

 

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watari
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Hi @systemsdeveloper 

 

Make sure utility buffer module.

There are some floating input on this module.

 

Best regards,

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@watari 

Not sure which Inputs you are refering in Utility buffer. 

BUFG_GT_I  Buffer input is connected,

BUFG_GT_CE  Buffer enable is connected to VCC logic 1

Not conected Inputs are BUFG_GT_CEMASK , BUFG_GT_CLR Asynchronous clear forcing the output to zero, BUFG_GT_CLRMASK CLR Mask,  BUFG_GT_DIV.  As fas as from IC  background, I see its a bug if xilinx SW ask for mendatory all additional inputs connection on utility buffer for generating wrong pl.dts.

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systemsdeveloper
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I can see dru-clk is routed in FPGA so I dont think Utility buffer unused inputs floating causing any issue to generate wrong pl.dts and unused pins connected to gnd too so looks ok to me.

 

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systemsdeveloper
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any thoughts from xilinx employee @kvasantr @samk 

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systemsdeveloper
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I reached to madness. I have transform Vivado design to  ZCU102 and build petalinux image file.

I can see "dru-clk" details in vid_phy_controller (in dts)  and "txref-clk" details in v_hdmi_tx_ss (dts). This means it correctly generating dts file for ZCU102 but it doesnt when I used for ZCU106 fpga. I dont have ZCU102 kit to test image but it is generating dts correctly.....

Sounds like bug in dts generation in SW for ZCU106 FPGA

Any suggestion on next step please.......

 

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@watari do you know "txref-clk" details in v_hdmi_tx_ss (pl.dts) is which clk in HDMI TX IP configuration? attached HDMI TX connection pic. "txref-clk" details is missing in pl.dts.

I guess its video-clk, its pixel clock lookslike from HDMI source code: xilinx_drm_hdmi.c

xhdmi->tmds_clk = devm_clk_get(&pdev->dev, "txref-clk");
if (IS_ERR(xhdmi->tmds_clk)) {
ret = PTR_ERR(xhdmi->tmds_clk);
xhdmi->tmds_clk = NULL;
if (ret == -EPROBE_DEFER)
dev_info(xhdmi->dev, "tx-clk not ready -EPROBE_DEFER\n");
if (ret != -EPROBE_DEFER)
dev_err(xhdmi->dev, "failed to get tx-clk.\n");
return ret;
}

hdmiTX_connection.PNG
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watari
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Hi @systemsdeveloper 

 

I guess it seems that there is the route cause in gt_refclk_buf and dru_ibufds_gt_odiv2.

Would you consider this clock path, again ?

 

Best regards,

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systemsdeveloper
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Thanks, I will have a look again and comeback to you. I am trying to rebuild from scratch.

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kvasantr
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Hello @systemsdeveloper 

Apologies for late reply on this. Allow me to answer two of your questions that you asked in your previous post:

(1) Why my auto-generated pl.dts file doesnt cover si570_2 & dru-clk information even when i have connected dru-clk select in IP configuration?

- We have this know issue with our DTG tool and we have an answer record that. you will need to make a manual device tree entry from system-user.dtsi to add this clocks. please refer following https://www.xilinx.com/support/answers/72454.html. Also we have this ready device tree entries available with our VCU TRD package in following path. W:\rdf0428-zcu106-vcu-trd-2019-2\apu\xilinx-vcu-zcu106-v2019.2-final\project-spec\meta-user\recipes-bsp\device-tree\files

we have steps to use those files in following wiki link.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/176914576/Zynq+UltraScale+MPSoC+VCU+TRD+2019.2+-+Run+and+Build+Flow

(2) How can I stop petalinux build to clean up HDMI source code after build? (I am adding  IMAGE_INSTALL_append = " kernel-module-hdmi" in meta-user/recipes-core/images/petalinux-image-full.bbappend) I would like to modify source code internally and want my build to use local checkout hdmi source code. 

Any ideas to solve this problem?

please use IMAGE_INTALL_remove instead of append. that should help resolve this query.

Regards

Kunal

-------------------------------------------------------------------------
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systemsdeveloper
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@kvasantr  Thank you so much.

I have add all missing details in system-user.dts

&amba_pl {
refhdmi: refhdmi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <114285000>;
};
dp159: hdmi-retimer@5e {
status = "okay";
compatible = "ti,dp159";
reg = <0x5e>;
#address-cell = <1>;
#size-cells = <0>;
#clocks-cells = <0>;
};
};

&zynq_us_ss_0_fmch_axi_iic {
si5324: clock-generator@68 {
status = "okay";
compatibility = "silabs.si5324";
reg = <0x68>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
clocks = <&refhdmi>;
clock-names = "xtal";
clk0 {
reg = <0>;
clock-frequency = <27000000>;
};
clk1 {
reg = <1>;
};
};
};

&v_hdmi_tx_ss {
clock-names = "s_axi_cpu_aclk", "link_clk", "s_axis_audio_aclk", "video_clk", "s_axis_video_aclk", "txref-clk", "re-timer";
clocks = <&zynqmp_clk 74>, <&misc_clk_0>, <&zynqmp_clk 74>, <&misc_clk_1>, <&zynqmp_clk 72>, <&si5324>, <&dp159>;
};

 

Successfully build device tree and rebuild image.

Now, I am moving forward but got this error "tx-clk not ready":

[ 5.116243] xilinx_vphy: loading out-of-tree module taints kernel.
[ 5.132876] xilinx-vphy 80060000.vid_phy_controller: probed
[ 5.139158] VPhy version : 02.02 (0000)
[ 5.149548] xilinx-vphy 80060000.vid_phy_controller: probe successful
[ 5.160036] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: probed
[ 5.166626] xvphy_phy_init((____ptrval____)).
[ 5.168474] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: probed
[ 5.171018] xvphy_phy_init((____ptrval____)).
[ 5.176281] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: hdmi tx audio disabled in DT
[ 5.180664] xvphy_phy_init((____ptrval____)).
[ 5.194343] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: tx-clk not ready -EPROBE_DEFER
[ 5.203554] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: Direct firmware load for xilinx/xilinx-hdmi-rx-edid.bin failed with error -2
[ 5.214982] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: Using Xilinx built-in EDID.
[ 5.222221]
[ 5.222221] Successfully loaded edid.
[ 5.227565] xilinx-video amba_pl@0:vcap_hdmi: Entity type for entity 80000000.v_hdmi_rx_ss was not initialized!
[ 5.239944] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: probe successful
[ 5.249561] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: probed
[ 5.254839] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: hdmi tx audio disabled in DT
[ 5.262047] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: tx-clk not ready -EPROBE_DEFER
[ 5.480798] FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
[ 5.507980] EXT4-fs (mmcblk0p2): recovery complete
[ 5.512840] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)

so not sure if anything wrong in system-user.dtsi.

Second thing:

as you said: please use IMAGE_INTALL_remove instead of append. that should help resolve this query.

I am using  2019.2, I tried but still build cleanup HDMI source after build.

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@kvasantr 

Further debugging:

I cant see probe called on Si5324 and dp159(re-timer) and stuck on v_hdmi_tx_ss: tx-clk not ready -EPROBE_DEFER.

and v_hdmi_tx_ss probe doesnt successful due to above error.

I am sure there is still something wrong with system-user.dts or its not properly overwriting dts property for given node.

Here is my full kernel log:

Starting kernel ...

[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[ 0.000000] Linux version 4.19.0-xilinx-v2019.2 (oe-user@oe-host) (gcc version 8.2.0 (GCC)) #1 SMP Tue Feb 18 13:32:30 UTC 2020
[ 0.000000] Machine model: ZynqMP ZCU106 RevA
[ 0.000000] earlycon: cdns0 at MMIO 0x00000000ff000000 (options '115200n8')
[ 0.000000] bootconsole [cdns0] enabled
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: UEFI not found.
[ 0.000000] cma: Reserved 256 MiB at 0x0000000068400000
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.1 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] psci: SMC Calling Convention v1.1
[ 0.000000] random: get_random_bytes called from start_kernel+0x94/0x3f8 with crng_init=0
[ 0.000000] percpu: Embedded 23 pages/cpu @(____ptrval____) s53656 r8192 d32360 u94208
[ 0.000000] Detected VIPT I-cache on CPU0
[ 0.000000] CPU features: enabling workaround for ARM erratum 845719
[ 0.000000] Speculative Store Bypass Disable mitigation not required
[ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1033987
[ 0.000000] Kernel command line: earlycon console=ttyPS0,115200 clk_ignore_unused
[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
[ 0.000000] software IO TLB: mapped [mem 0x7beff000-0x7feff000] (64MB)
[ 0.000000] Memory: 3772772K/4193280K available (10748K kernel code, 634K rwdata, 5416K rodata, 832K init, 314K bss, 158364K reserved, 262144K cma-reserved)
[ 0.000000] rcu: Hierarchical RCU implementation.
[ 0.000000] rcu: RCU event tracing is enabled.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] arch_timer: cp15 timer(s) running at 99.99MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x170f8de2d3, max_idle_ns: 440795206112 ns
[ 0.000003] sched_clock: 56 bits at 99MHz, resolution 10ns, wraps every 4398046511101ns
[ 0.008276] Console: colour dummy device 80x25
[ 0.012394] Calibrating delay loop (skipped), value calculated using timer frequency.. 199.98 BogoMIPS (lpj=399960)
[ 0.022757] pid_max: default: 32768 minimum: 301
[ 0.027451] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes)
[ 0.034013] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes)
[ 0.041809] ASID allocator initialised with 32768 entries
[ 0.046508] rcu: Hierarchical SRCU implementation.
[ 0.051560] EFI services will not be available.
[ 0.055828] smp: Bringing up secondary CPUs ...
[ 0.060489] Detected VIPT I-cache on CPU1
[ 0.060517] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[ 0.060821] Detected VIPT I-cache on CPU2
[ 0.060839] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
[ 0.061124] Detected VIPT I-cache on CPU3
[ 0.061144] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
[ 0.061187] smp: Brought up 1 node, 4 CPUs
[ 0.095682] SMP: Total of 4 processors activated.
[ 0.100356] CPU features: detected: 32-bit EL0 Support
[ 0.106992] CPU: All CPU(s) started at EL2
[ 0.109535] alternatives: patching kernel code
[ 0.114807] devtmpfs: initialized
[ 0.122440] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.126921] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 0.138601] xor: measuring software checksum speed
[ 0.177126] 8regs : 2375.000 MB/sec
[ 0.217154] 8regs_prefetch: 2052.000 MB/sec
[ 0.257182] 32regs : 2724.000 MB/sec
[ 0.297212] 32regs_prefetch: 2308.000 MB/sec
[ 0.297252] xor: using function: 32regs (2724.000 MB/sec)
[ 0.301563] pinctrl core: initialized pinctrl subsystem
[ 0.307376] NET: Registered protocol family 16
[ 0.311400] audit: initializing netlink subsys (disabled)
[ 0.316594] audit: type=2000 audit(0.268:1): state=initialized audit_enabled=0 res=1
[ 0.324244] cpuidle: using governor menu
[ 0.328221] vdso: 2 pages (1 code @ (____ptrval____), 1 data @ (____ptrval____))
[ 0.335470] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[ 0.342891] DMA: preallocated 256 KiB pool for atomic allocations
[ 0.362872] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[ 0.430934] raid6: int64x1 gen() 447 MB/s
[ 0.498972] raid6: int64x1 xor() 450 MB/s
[ 0.566995] raid6: int64x2 gen() 681 MB/s
[ 0.635045] raid6: int64x2 xor() 599 MB/s
[ 0.703061] raid6: int64x4 gen() 980 MB/s
[ 0.771109] raid6: int64x4 xor() 736 MB/s
[ 0.839165] raid6: int64x8 gen() 1163 MB/s
[ 0.907199] raid6: int64x8 xor() 759 MB/s
[ 0.975290] raid6: neonx1 gen() 735 MB/s
[ 1.043292] raid6: neonx1 xor() 879 MB/s
[ 1.111343] raid6: neonx2 gen() 1129 MB/s
[ 1.179398] raid6: neonx2 xor() 1172 MB/s
[ 1.247434] raid6: neonx4 gen() 1479 MB/s
[ 1.315473] raid6: neonx4 xor() 1416 MB/s
[ 1.383551] raid6: neonx8 gen() 1536 MB/s
[ 1.451573] raid6: neonx8 xor() 1460 MB/s
[ 1.451611] raid6: using algorithm neonx8 gen() 1536 MB/s
[ 1.455563] raid6: .... xor() 1460 MB/s, rmw enabled
[ 1.460494] raid6: using neon recovery algorithm
[ 1.465908] SCSI subsystem initialized
[ 1.468971] usbcore: registered new interface driver usbfs
[ 1.474284] usbcore: registered new interface driver hub
[ 1.479554] usbcore: registered new device driver usb
[ 1.484606] media: Linux media interface: v0.10
[ 1.489063] videodev: Linux video capture interface: v2.00
[ 1.494514] pps_core: LinuxPPS API ver. 1 registered
[ 1.499424] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 1.508517] PTP clock support registered
[ 1.512416] EDAC MC: Ver: 3.0.0
[ 1.515900] zynqmp-ipi-mbox mailbox@ff990400: Probed ZynqMP IPI Mailbox driver.
[ 1.523066] FPGA manager framework
[ 1.526322] Advanced Linux Sound Architecture Driver Initialized.
[ 1.532481] Bluetooth: Core ver 2.22
[ 1.535771] NET: Registered protocol family 31
[ 1.540171] Bluetooth: HCI device and connection manager initialized
[ 1.546487] Bluetooth: HCI socket layer initialized
[ 1.551330] Bluetooth: L2CAP socket layer initialized
[ 1.556362] Bluetooth: SCO socket layer initialized
[ 1.561483] clocksource: Switched to clocksource arch_sys_counter
[ 1.567327] VFS: Disk quotas dquot_6.6.0
[ 1.571182] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 1.582268] NET: Registered protocol family 2
[ 1.582662] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes)
[ 1.590127] TCP established hash table entries: 32768 (order: 6, 262144 bytes)
[ 1.597471] TCP bind hash table entries: 32768 (order: 7, 524288 bytes)
[ 1.604241] TCP: Hash tables configured (established 32768 bind 32768)
[ 1.610387] UDP hash table entries: 2048 (order: 4, 65536 bytes)
[ 1.616367] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes)
[ 1.622847] NET: Registered protocol family 1
[ 1.627241] RPC: Registered named UNIX socket transport module.
[ 1.632912] RPC: Registered udp transport module.
[ 1.637580] RPC: Registered tcp transport module.
[ 1.642251] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 1.648989] Trying to unpack rootfs image as initramfs...
[ 2.066687] Freeing initrd memory: 9912K
[ 2.067077] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[ 2.072233] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
[ 2.080767] Initialise system trusted keyrings
[ 2.084254] workingset: timestamp_bits=62 max_order=20 bucket_order=0
[ 2.091274] NFS: Registering the id_resolver key type
[ 2.095617] Key type id_resolver registered
[ 2.099752] Key type id_legacy registered
[ 2.103736] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[ 2.110404] jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
[ 3.204392] NET: Registered protocol family 38
[ 3.265287] Key type asymmetric registered
[ 3.265325] Asymmetric key parser 'x509' registered
[ 3.268642] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
[ 3.275944] io scheduler noop registered
[ 3.279833] io scheduler deadline registered
[ 3.284105] io scheduler cfq registered (default)
[ 3.288744] io scheduler mq-deadline registered
[ 3.293241] io scheduler kyber registered
[ 3.298996] xilinx-frmbuf 80010000.v_frmbuf_rd: failed to get ap_clk (-517)
[ 3.304178] xilinx-frmbuf 80050000.v_frmbuf_wr: failed to get ap_clk (-517)
[ 3.337534] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 3.342120] xlnx-pl-disp amba_pl@0:drm-dmaengine-drv: failed to request dma channel
[ 3.346132] cacheinfo: Unable to detect cache hierarchy for CPU 0
[ 3.356416] brd: module loaded
[ 3.360237] loop: module loaded
[ 3.361152] mtdoops: mtd device (mtddev=name/number) must be supplied
[ 3.365879] libphy: Fixed MDIO Bus: probed
[ 3.369774] tun: Universal TUN/TAP device driver, 1.6
[ 3.373659] CAN device driver interface
[ 3.378533] usbcore: registered new interface driver asix
[ 3.382752] usbcore: registered new interface driver ax88179_178a
[ 3.388798] usbcore: registered new interface driver cdc_ether
[ 3.394592] usbcore: registered new interface driver net1080
[ 3.400215] usbcore: registered new interface driver cdc_subset
[ 3.406097] usbcore: registered new interface driver zaurus
[ 3.411643] usbcore: registered new interface driver cdc_ncm
[ 3.418116] usbcore: registered new interface driver uas
[ 3.422544] usbcore: registered new interface driver usb-storage
[ 3.429024] rtc_zynqmp ffa60000.rtc: rtc core: registered ffa60000.rtc as rtc0
[ 3.435729] i2c /dev entries driver
[ 3.439551] xilinx-video amba_pl@0:vcap_hdmi: /amba_pl@0/vcap_hdmi/ports/port@0 initialization failed
[ 3.448294] xilinx-video amba_pl@0:vcap_hdmi: DMA initialization failed
[ 3.456496] usbcore: registered new interface driver uvcvideo
[ 3.460576] USB Video Class driver (1.1.1)
[ 3.465714] Bluetooth: HCI UART driver ver 2.3
[ 3.469050] Bluetooth: HCI UART protocol H4 registered
[ 3.474162] Bluetooth: HCI UART protocol BCSP registered
[ 3.479455] Bluetooth: HCI UART protocol LL registered
[ 3.484538] Bluetooth: HCI UART protocol ATH3K registered
[ 3.489918] Bluetooth: HCI UART protocol Three-wire (H5) registered
[ 3.496173] Bluetooth: HCI UART protocol Intel registered
[ 3.501511] Bluetooth: HCI UART protocol QCA registered
[ 3.506716] usbcore: registered new interface driver bcm203x
[ 3.512336] usbcore: registered new interface driver bpa10x
[ 3.517875] usbcore: registered new interface driver bfusb
[ 3.523322] usbcore: registered new interface driver btusb
[ 3.528745] Bluetooth: Generic Bluetooth SDIO driver ver 0.1
[ 3.534412] usbcore: registered new interface driver ath3k
[ 3.539945] EDAC MC: ECC not enabled
[ 3.543584] EDAC DEVICE0: Giving out device to module zynqmp-ocm-edac controller zynqmp_ocm: DEV ff960000.memory-controller (INTERRUPT)
[ 3.556198] sdhci: Secure Digital Host Controller Interface driver
[ 3.561618] sdhci: Copyright(c) Pierre Ossman
[ 3.565942] sdhci-pltfm: SDHCI platform and OF driver helper
[ 3.571921] ledtrig-cpu: registered to indicate activity on CPUs
[ 3.577586] zynqmp_firmware_probe Platform Management API v1.1
[ 3.583333] zynqmp_firmware_probe Trustzone version v1.0
[ 3.591334] zynqmp-pinctrl firmware:zynqmp-firmware:pinctrl: zynqmp pinctrl initialized
[ 3.619606] zynqmp_clk_mux_get_parent() getparent failed for clock: lpd_wdt, ret = -22
[ 3.622345] alg: No test for xilinx-zynqmp-aes (zynqmp-aes)
[ 3.627515] zynqmp_aes zynqmp_aes: AES Successfully Registered
[ 3.627515]
[ 3.634965] alg: No test for xilinx-keccak-384 (zynqmp-keccak-384)
[ 3.641116] alg: No test for xilinx-zynqmp-rsa (zynqmp-rsa)
[ 3.646656] usbcore: registered new interface driver usbhid
[ 3.651979] usbhid: USB HID core driver
[ 3.658162] fpga_manager fpga0: Xilinx ZynqMP FPGA Manager registered
[ 3.662598] usbcore: registered new interface driver snd-usb-audio
[ 3.669318] pktgen: Packet Generator for packet performance testing. Version: 2.75
[ 3.676227] Initializing XFRM netlink socket
[ 3.680168] NET: Registered protocol family 10
[ 3.684851] Segment Routing with IPv6
[ 3.688222] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[ 3.694347] NET: Registered protocol family 17
[ 3.698442] NET: Registered protocol family 15
[ 3.702854] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
[ 3.715770] can: controller area network core (rev 20170425 abi 9)
[ 3.721904] NET: Registered protocol family 29
[ 3.726289] can: raw protocol (rev 20170425)
[ 3.730525] can: broadcast manager protocol (rev 20170425 t)
[ 3.736150] can: netlink gateway (rev 20170425) max_hops=1
[ 3.741824] Bluetooth: RFCOMM TTY layer initialized
[ 3.746451] Bluetooth: RFCOMM socket layer initialized
[ 3.751557] Bluetooth: RFCOMM ver 1.11
[ 3.755271] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[ 3.760543] Bluetooth: BNEP filters: protocol multicast
[ 3.765736] Bluetooth: BNEP socket layer initialized
[ 3.770665] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[ 3.776549] Bluetooth: HIDP socket layer initialized
[ 3.781604] 9pnet: Installing 9P2000 support
[ 3.785732] Key type dns_resolver registered
[ 3.790329] registered taskstats version 1
[ 3.794027] Loading compiled-in X.509 certificates
[ 3.799105] Btrfs loaded, crc32c=crc32c-generic
[ 3.809664] ff000000.serial: ttyPS0 at MMIO 0xff000000 (irq = 41, base_baud = 6249375) is a xuartps
[ 3.819506] console [ttyPS0] enabled
[ 3.819506] console [ttyPS0] enabled
[ 3.823105] bootconsole [cdns0] disabled
[ 3.823105] bootconsole [cdns0] disabled
[ 3.831865] of-fpga-region fpga-full: FPGA Region probed
[ 3.840358] xilinx-zynqmp-dma fd500000.dma: ZynqMP DMA driver Probe success
[ 3.847466] xilinx-zynqmp-dma fd510000.dma: ZynqMP DMA driver Probe success
[ 3.854575] xilinx-zynqmp-dma fd520000.dma: ZynqMP DMA driver Probe success
[ 3.861679] xilinx-zynqmp-dma fd530000.dma: ZynqMP DMA driver Probe success
[ 3.868785] xilinx-zynqmp-dma fd540000.dma: ZynqMP DMA driver Probe success
[ 3.875892] xilinx-zynqmp-dma fd550000.dma: ZynqMP DMA driver Probe success
[ 3.882996] xilinx-zynqmp-dma fd560000.dma: ZynqMP DMA driver Probe success
[ 3.890102] xilinx-zynqmp-dma fd570000.dma: ZynqMP DMA driver Probe success
[ 3.897283] xilinx-zynqmp-dma ffa80000.dma: ZynqMP DMA driver Probe success
[ 3.904386] xilinx-zynqmp-dma ffa90000.dma: ZynqMP DMA driver Probe success
[ 3.911492] xilinx-zynqmp-dma ffaa0000.dma: ZynqMP DMA driver Probe success
[ 3.918594] xilinx-zynqmp-dma ffab0000.dma: ZynqMP DMA driver Probe success
[ 3.925694] xilinx-zynqmp-dma ffac0000.dma: ZynqMP DMA driver Probe success
[ 3.932795] xilinx-zynqmp-dma ffad0000.dma: ZynqMP DMA driver Probe success
[ 3.939897] xilinx-zynqmp-dma ffae0000.dma: ZynqMP DMA driver Probe success
[ 3.947001] xilinx-zynqmp-dma ffaf0000.dma: ZynqMP DMA driver Probe success
[ 3.954102] xilinx-frmbuf 80010000.v_frmbuf_rd: Xilinx AXI frmbuf DMA_MEM_TO_DEV
[ 3.961554] xilinx-frmbuf 80010000.v_frmbuf_rd: Xilinx AXI FrameBuffer Engine Driver Probed!!
[ 3.970200] xilinx-frmbuf 80050000.v_frmbuf_wr: Xilinx AXI frmbuf DMA_DEV_TO_MEM
[ 3.977651] xilinx-frmbuf 80050000.v_frmbuf_wr: Xilinx AXI FrameBuffer Engine Driver Probed!!
[ 3.986303] xlnx-pl-disp amba_pl@0:drm-dmaengine-drv: vtc bridge property not present
[ 3.994227] xlnx-pl-disp amba_pl@0:drm-dmaengine-drv: Xlnx PL display driver probed
[ 4.002871] m25p80 spi0.0: n25q512a (131072 Kbytes)
[ 4.007766] 3 fixed-partitions partitions found on MTD device spi0.0
[ 4.014117] Creating 3 MTD partitions on "spi0.0":
[ 4.018901] 0x000000000000-0x000000100000 : "boot"
[ 4.024093] zynqmp_pll_disable() clock disable failed for apll_int, ret = -13
[ 4.031376] 0x000000100000-0x000000140000 : "bootenv"
[ 4.036828] 0x000000140000-0x000001740000 : "kernel"
[ 4.044232] macb ff0e0000.ethernet: Not enabling partial store and forward
[ 4.051591] libphy: MACB_mii_bus: probed
[ 4.060596] TI DP83867 ff0e0000.ethernet-ffffffff:0c: attached PHY driver [TI DP83867] (mii_bus:phy_addr=ff0e0000.ethernet-ffffffff:0c, irq=POLL)
[ 4.073646] macb ff0e0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0e0000 irq 30 (00:0a:35:00:22:01)
[ 4.083854] xilinx-axipmon ffa00000.perf-monitor: Probed Xilinx APM
[ 4.090413] xilinx-axipmon fd0b0000.perf-monitor: Probed Xilinx APM
[ 4.096908] xilinx-axipmon fd490000.perf-monitor: Probed Xilinx APM
[ 4.103389] xilinx-axipmon ffa10000.perf-monitor: Probed Xilinx APM
[ 4.110551] pca953x 0-0020: 0-0020 supply vcc not found, using dummy regulator
[ 4.117799] pca953x 0-0020: Linked as a consumer to regulator.0
[ 4.124386] pca953x 0-0021: 0-0021 supply vcc not found, using dummy regulator
[ 4.131635] pca953x 0-0021: Linked as a consumer to regulator.0
[ 4.138960] ina2xx 3-0040: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.145743] ina2xx 3-0041: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.152526] ina2xx 3-0042: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.159308] ina2xx 3-0043: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.166098] ina2xx 3-0044: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.172884] ina2xx 3-0045: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.179676] ina2xx 3-0046: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.186466] ina2xx 3-0047: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.193253] ina2xx 3-004a: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.200046] ina2xx 3-004b: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.206429] i2c i2c-0: Added multiplexed i2c bus 3
[ 4.211836] ina2xx 4-0040: power monitor ina226 (Rshunt = 2000 uOhm)
[ 4.218631] ina2xx 4-0041: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.225411] ina2xx 4-0042: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.232194] ina2xx 4-0043: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.238985] ina2xx 4-0044: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.245768] ina2xx 4-0045: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.252559] ina2xx 4-0046: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.259346] ina2xx 4-0047: power monitor ina226 (Rshunt = 5000 uOhm)
[ 4.265726] i2c i2c-0: Added multiplexed i2c bus 4
[ 4.287939] random: fast init done
[ 4.306974] i2c i2c-0: Added multiplexed i2c bus 5
[ 4.311888] i2c i2c-0: Added multiplexed i2c bus 6
[ 4.316675] pca954x 0-0075: registered 4 multiplexed busses for I2C mux pca9544
[ 4.324010] cdns-i2c ff020000.i2c: 400 kHz mmio ff020000 irq 32
[ 4.331704] at24 7-0054: 1024 byte 24c08 EEPROM, writable, 1 bytes/write
[ 4.338429] i2c i2c-1: Added multiplexed i2c bus 7
[ 4.343424] i2c i2c-1: Added multiplexed i2c bus 8
[ 4.350295] si570 9-005d: registered, current frequency 300000000 Hz
[ 4.356679] i2c i2c-1: Added multiplexed i2c bus 9
[ 4.373489] si570 10-005d: registered, current frequency 148500000 Hz
[ 4.379949] i2c i2c-1: Added multiplexed i2c bus 10
[ 4.385017] si5324 11-0069: si5328 probed
[ 4.445780] si5324 11-0069: si5328 probe successful
[ 4.450683] i2c i2c-1: Added multiplexed i2c bus 11
[ 4.455768] i2c i2c-1: Added multiplexed i2c bus 12
[ 4.460774] i2c i2c-1: Added multiplexed i2c bus 13
[ 4.465768] i2c i2c-1: Added multiplexed i2c bus 14
[ 4.470648] pca954x 1-0074: registered 8 multiplexed busses for I2C switch pca9548
[ 4.478551] i2c i2c-1: Added multiplexed i2c bus 15
[ 4.483554] i2c i2c-1: Added multiplexed i2c bus 16
[ 4.488554] i2c i2c-1: Added multiplexed i2c bus 17
[ 4.493943] i2c i2c-1: Added multiplexed i2c bus 18
[ 4.498952] i2c i2c-1: Added multiplexed i2c bus 19
[ 4.503958] i2c i2c-1: Added multiplexed i2c bus 20
[ 4.508963] i2c i2c-1: Added multiplexed i2c bus 21
[ 4.513963] i2c i2c-1: Added multiplexed i2c bus 22
[ 4.518836] pca954x 1-0075: registered 8 multiplexed busses for I2C switch pca9548
[ 4.526427] cdns-i2c ff030000.i2c: 400 kHz mmio ff030000 irq 33
[ 4.533062] i2c i2c-2: of_i2c: modalias failure on /amba_pl@0/i2c@80041000/clock-generator@68
[ 4.541593] i2c i2c-2: Failed to create I2C device for /amba_pl@0/i2c@80041000/clock-generator@68
[ 4.550752] xilinx-video amba_pl@0:vcap_hdmi: device registered
[ 4.559563] cdns-wdt fd4d0000.watchdog: Xilinx Watchdog Timer with timeout 60s
[ 4.567000] cdns-wdt ff150000.watchdog: Xilinx Watchdog Timer with timeout 10s
[ 4.574504] cpufreq: cpufreq_online: CPU0: Running at unlisted freq: 1199880 KHz
[ 4.581955] cpufreq: cpufreq_online: CPU0: Unlisted initial frequency changed to: 1199999 KHz
[ 4.621488] mmc0: SDHCI controller on ff170000.mmc [ff170000.mmc] using ADMA 64-bit
[ 4.642630] input: gpio-keys as /devices/platform/gpio-keys/input/input0
[ 4.649596] rtc_zynqmp ffa60000.rtc: setting system clock to 2020-02-18 16:52:38 UTC (1582044758)
[ 4.658469] of_cfs_init
[ 4.660918] of_cfs_init: OK
[ 4.663840] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[ 4.731997] mmc0: new ultra high speed DDR50 SDHC card at address aaaa
[ 4.739070] mmcblk0: mmc0:aaaa SL16G 14.8 GiB
[ 4.748295] mmcblk0: p1 p2
[ 4.808361] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[ 4.814890] clk: Not disabling unused clocks
[ 4.819159] ALSA device list:
[ 4.822120] No soundcards found.
[ 4.825798] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[ 4.834411] cfg80211: failed to load regulatory.db
[ 4.839670] Freeing unused kernel memory: 832K
[ 4.865517] Run /init as init process
INIT: version 2.88 booting
Starting udev
[ 4.988654] udevd[1946]: starting version 3.2.5
[ 4.993537] random: udevd: uninitialized urandom read (16 bytes read)
[ 5.000030] random: udevd: uninitialized urandom read (16 bytes read)
[ 5.006525] random: udevd: uninitialized urandom read (16 bytes read)
[ 5.017014] udevd[1947]: starting eudev-3.2.5
[ 5.118692] dp159: loading out-of-tree module taints kernel.
[ 5.120280] xilinx_vphy: loading out-of-tree module taints kernel.
[ 5.149800] xilinx-vphy 80060000.vid_phy_controller: probed
[ 5.164189] VPhy version : 02.02 (0000)
[ 5.174041] xilinx-vphy 80060000.vid_phy_controller: probe successful
[ 5.184929] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: probed
[ 5.190205] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: hdmi tx audio disabled in DT
[ 5.197385] xvphy_phy_init((____ptrval____)).
[ 5.201756] xvphy_phy_init((____ptrval____)).
[ 5.206149] xvphy_phy_init((____ptrval____)).
[ 5.210546] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: tx-clk not ready -EPROBE_DEFER
[ 5.219693] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: probed
[ 5.234344] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: Direct firmware load for xilinx/xilinx-hdmi-rx-edid.bin failed with error -2
[ 5.245772] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: Using Xilinx built-in EDID.
[ 5.253023]
[ 5.253023] Successfully loaded edid.
[ 5.258359] xilinx-video amba_pl@0:vcap_hdmi: Entity type for entity 80000000.v_hdmi_rx_ss was not initialized!
[ 5.282420] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: probe successful
[ 5.292495] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: probed
[ 5.297798] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: hdmi tx audio disabled in DT
[ 5.305027] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: tx-clk not ready -EPROBE_DEFER
[ 5.512313] EXT4-fs (mmcblk0p2): recovery complete
[ 5.517118] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
[ 5.519520] FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
Configuring packages on first boot....
(This may take several minutes. Please do not power off the machine.)
Running postinst /etc/rpm-postinsts/100-sysvinit-inittab...
update-rc.d: /etc/init.d/run-postinsts exists during rc.d purge (continuing)
INIT: Entering runlevel: 5
Configuring network interfaces... [ 5.962035] pps pps0: new PPS source ptp0
[ 5.966054] macb ff0e0000.ethernet: gem-ptp-timer ptp clock registered.
[ 5.972757] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
udhcpc: started, v1.29.2
udhcpc: sending discover
udhcpc: sending discover

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systemsdeveloper
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Registered: ‎06-10-2019

made little progress with correcting node dp159, moved under zynq_us_ss_0_fmch_axi_iic.

So I manage to get dp159 probe successfully but still throwing error on tx-clk not ready -EPROBE_DEFER and doesnt probe Si5324.  Any idea?

Updated system-user.dtsi :

&amba_pl {
refhdmi: refhdmi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <114285000>;
};

};

&zynq_us_ss_0_fmch_axi_iic {
si5324: clock-generator@68 {
status = "okay";
compatibility = "silabs.si5324";
reg = <0x68>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
clocks = <&refhdmi>;
clock-names = "xtal";
clk0 {
reg = <0>;
clock-frequency = <27000000>;
};
clk1 {
reg = <1>;
};
};

dp159: hdmi-retimer@5e {
status = "okay";
compatible = "ti,dp159";
reg = <0x5e>;
#address-cell = <1>;
#size-cells = <0>;
#clocks-cells = <0>;
};
};

&v_hdmi_tx_ss {
clock-names = "s_axi_cpu_aclk", "link_clk", "s_axis_audio_aclk", "video_clk", "s_axis_video_aclk", "txref-clk", "re-timer";
clocks = <&zynqmp_clk 74>, <&misc_clk_0>, <&zynqmp_clk 74>, <&misc_clk_1>, <&zynqmp_clk 72>, <&si5324>, <&dp159>;
};

Log suggested failing on clock:

[ 4.372228] pca954x 1-0074: registered 8 multiplexed busses for I2C switch pca9548
[ 4.380130] i2c i2c-1: Added multiplexed i2c bus 14
[ 4.385138] i2c i2c-1: Added multiplexed i2c bus 15
[ 4.390138] i2c i2c-1: Added multiplexed i2c bus 16
[ 4.395514] i2c i2c-1: Added multiplexed i2c bus 17
[ 4.400514] i2c i2c-1: Added multiplexed i2c bus 18
[ 4.405523] i2c i2c-1: Added multiplexed i2c bus 19
[ 4.410525] i2c i2c-1: Added multiplexed i2c bus 20
[ 4.415526] i2c i2c-1: Added multiplexed i2c bus 21
[ 4.420405] pca954x 1-0075: registered 8 multiplexed busses for I2C switch pca9548
[ 4.427997] cdns-i2c ff030000.i2c: 400 kHz mmio ff030000 irq 33
[ 4.434426] i2c i2c-22: of_i2c: modalias failure on /amba_pl@0/i2c@80041000/clock-generator@68
[ 4.443038] i2c i2c-22: Failed to create I2C device for /amba_pl@0/i2c@80041000/clock-generator@68

HDMI log:

[ 4.908835] random: udevd: uninitialized urandom read (16 bytes read)
[ 4.915335] random: udevd: uninitialized urandom read (16 bytes read)
[ 4.921835] random: udevd: uninitialized urandom read (16 bytes read)
[ 4.932421] udevd[1968]: starting eudev-3.2.5
[ 5.044610] xilinx_vphy: loading out-of-tree module taints kernel.
[ 5.044612] xilinx_vphy: loading out-of-tree module taints kernel.
[ 5.057741] xilinx-vphy 80060000.vid_phy_controller: probed
[ 5.065961] dp159 22-005e: probed
[ 5.067315] VPhy version : 02.02 (0000)
[ 5.070904] dp159 22-005e: probe successful
[ 5.074429] xilinx-vphy 80060000.vid_phy_controller: probe successful
[ 5.088267] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: probed
[ 5.094012] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: probed
[ 5.098660] xvphy_phy_init((____ptrval____)).
[ 5.099294] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: hdmi tx audio disabled in DT
[ 5.103618] xvphy_phy_init((____ptrval____)).
[ 5.115199] xvphy_phy_init((____ptrval____)).
[ 5.119622] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: tx-clk not ready -EPROBE_DEFER
[ 5.131169] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: Direct firmware load for xilinx/xilinx-hdmi-rx-edid.bin failed with error -2
[ 5.142610] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: Using Xilinx built-in EDID.
[ 5.149834]
[ 5.149834] Successfully loaded edid.
[ 5.155162] xilinx-video amba_pl@0:vcap_hdmi: Entity type for entity 80000000.v_hdmi_rx_ss was not initialized!
[ 5.165599] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: probe successful
[ 5.176327] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: probed
[ 5.181616] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: hdmi tx audio disabled in DT
[ 5.188877] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: tx-clk not ready -EPROBE_DEFER
[ 5.407582] EXT4-fs (mmcblk0p2): recovery complete
[ 5.412544] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
[ 5.434353] FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.

 

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systemsdeveloper
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Clsoing this issue with summary:

As earlier, kvasantr said , its bug in DTG generation tool so Auto generated pl.dtsi doesnt have any details about "txref-clk","dru-clk" and "retimer-clk" with Si5324 and dp159 details. lake of this details in DTS will stop you @ HDMI TX/RX driver probe doesnt succeed. Lots of time wasted because of bug in tools.

lets back to Solutions as suggested, add all those entry in system-user.dtsi or you can stop including pl.dtsi in your build(--get-hw-description ->DTG generation->remove pl device tree from build) and add all your entry in system-user.dtsi.

my last two posts was on various issue on dtsi because it was my BAD typo mistake in system-user.dtsi when itried manually adding all entries.

final system-user-dtsi:

&amba_pl {
refhdmi: refhdmi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <114285000>;
};
 dp159: hdmi-retimer@5e {
status = "okay";
compatible = "ti,dp159";
reg = <0x5e>;
#address-cell = <1>;
#size-cells = <0>;
#clock-cells = <0>;
};
};

&zynq_us_ss_0_fmch_axi_iic {
 si5324: clock-generator@68 {
status = "okay";
compatible = "silabs,si5324";
reg = <68>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
clocks = <&refhdmi>;
clock-names = "xtal";
clk0 {
reg = <0>;
clock-frequency = <27000000>;
};
};

&v_hdmi_tx_ss {
 clock-names = "s_axi_cpu_aclk", "link_clk", "s_axis_audio_aclk", "video_clk", "s_axis_video_aclk", "txref-clk", "retimer-clk";
clocks = <&zynqmp_clk 74>, <&misc_clk_0>, <&zynqmp_clk 74>, <&misc_clk_1>, <&zynqmp_clk 72>, <&si5324 0>, <&dp159>;
};

As explained above second option, first build system with pl.dtsi than copy file somewhere and modify manually than build again with remove pl.dtsi. finally add all entry in system-user.dtsi(may be not great option but it works)

Now syste,-user.dtsi looks like:

/include/ "system-conf.dtsi"

/ {
amba_pl: amba_pl@0 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges ;
v_frmbuf_rd_0: v_frmbuf_rd@80010000 {
#dma-cells = <1>;
clock-names = "ap_clk";
clocks = <&zynqmp_clk 72>;
compatible = "xlnx,v-frmbuf-rd-2.1", "xlnx,axi-frmbuf-rd-v2.1";
interrupt-names = "interrupt";
interrupt-parent = <&gic>;
interrupts = <0 93 4>;
reg = <0x0 0x80010000 0x0 0x10000>;
reset-gpios = <&gpio 79 1>;
xlnx,dma-addr-width = <64>;
xlnx,dma-align = <16>;
xlnx,fid ;
xlnx,max-height = <2160>;
xlnx,max-width = <3840>;
xlnx,pixels-per-clock = <2>;
xlnx,s-axi-ctrl-addr-width = <0x7>;
xlnx,s-axi-ctrl-data-width = <0x20>;
xlnx,vid-formats = "rgb888", "xbgr8888", "xrgb8888", "bgr888", "uyvy", "y8", "vuy888", "xvuy8888", "yuyv", "nv12", "nv16";
xlnx,video-width = <8>;
};
v_frmbuf_wr_0: v_frmbuf_wr@80050000 {
#dma-cells = <1>;
clock-names = "ap_clk";
clocks = <&zynqmp_clk 72>;
compatible = "xlnx,v-frmbuf-wr-2.1", "xlnx,axi-frmbuf-wr-v2.1";
interrupt-names = "interrupt";
interrupt-parent = <&gic>;
interrupts = <0 92 4>;
reg = <0x0 0x80050000 0x0 0x10000>;
reset-gpios = <&gpio 78 1>;
xlnx,dma-addr-width = <64>;
xlnx,dma-align = <16>;
xlnx,fid ;
xlnx,max-height = <2160>;
xlnx,max-width = <3840>;
xlnx,pixels-per-clock = <2>;
xlnx,s-axi-ctrl-addr-width = <0x7>;
xlnx,s-axi-ctrl-data-width = <0x20>;
xlnx,vid-formats = "rgb888", "bgr888", "xbgr8888", "xrgb8888", "uyvy", "y8", "vuy888", "xvuy8888", "yuyv", "nv12", "nv16";
xlnx,video-width = <8>;
};
v_hdmi_rx_ss: v_hdmi_rx_ss@80000000 {
clock-names = "s_axi_cpu_aclk", "link_clk", "s_axis_audio_aclk", "video_clk", "s_axis_video_aclk";
clocks = <&zynqmp_clk 74>, <&misc_clk_0>, <&zynqmp_clk 74>, <&misc_clk_1>, <&zynqmp_clk 72>;
compatible = "xlnx,v-hdmi-rx-ss-3.1", "xlnx,v-hdmi-rx-ss-3.1";
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 90 4>;
phy-names = "hdmi-phy0", "hdmi-phy1", "hdmi-phy2";
phys = <&vphy_lane0 0 1 1 0>, <&vphy_lane1 0 1 1 0>, <&vphy_lane2 0 1 1 0>;
reg = <0x0 0x80000000 0x0 0x10000>;
xlnx,edid-ram-size = <0x100>;
xlnx,input-pixels-per-clock = <2>;
xlnx,max-bits-per-component = <8>;
hdmirx_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
hdmirx_port: port@0 {
reg = <0>;
hdmi_rx_out: endpoint {
remote-endpoint = <&vcap_hdmi_in>;
};
};
};
};
misc_clk_0: misc_clk_0 {
#clock-cells = <0>;
clock-frequency = <148500000>;
compatible = "fixed-clock";
};
misc_clk_1: misc_clk_1 {
#clock-cells = <0>;
clock-frequency = <297000000>;
compatible = "fixed-clock";
};

v_hdmi_tx_ss: v_hdmi_tx_ss@80020000 {
clock-names = "s_axi_cpu_aclk", "link_clk", "s_axis_audio_aclk", "video_clk", "s_axis_video_aclk", "txref-clk", "retimer-clk";
clocks = <&zynqmp_clk 74>, <&misc_clk_0>, <&zynqmp_clk 74>, <&misc_clk_1>, <&zynqmp_clk 72>, <&si5324 0>, <&dp159>;
compatible = "xlnx,v-hdmi-tx-ss-3.1", "xlnx,v-hdmi-tx-ss-3.1";
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 91 4>;
phy-names = "hdmi-phy0", "hdmi-phy1", "hdmi-phy2";
phys = <&vphy_lane0 0 1 1 1>, <&vphy_lane1 0 1 1 1>, <&vphy_lane2 0 1 1 1>;
reg = <0x0 0x80020000 0x0 0x20000>;
xlnx,input-pixels-per-clock = <2>;
xlnx,max-bits-per-component = <8>;
hdmitx_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
encoder_hdmi_port: port@0 {
reg = <0>;
hdmi_encoder: endpoint {
remote-endpoint = <&dmaengine_crtc>;
};
};
};
};
vid_phy_controller: vid_phy_controller@80060000 {
clock-names = "mgtrefclk0_pad_p_in", "mgtrefclk0_pad_n_in", "mgtrefclk1_pad_p_in", "mgtrefclk1_pad_n_in", "vid_phy_tx_axi4s_aclk", "vid_phy_rx_axi4s_aclk", "vid_phy_sb_aclk", "vid_phy_axi4lite_aclk", "drpclk";
clocks = <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_0>, <&zynqmp_clk 74>, <&zynqmp_clk 74>, <&zynqmp_clk 74>;
compatible = "xlnx,vid-phy-controller-2.2", "xlnx,vid-phy-controller-2.1";
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 89 4>;
reg = <0x0 0x80060000 0x0 0x10000>;
xlnx,hdmi-fast-switch = <1>;
xlnx,input-pixels-per-clock = <2>;
xlnx,nidru = <0>;
xlnx,nidru-refclk-sel = <4>;
xlnx,rx-no-of-channels = <3>;
xlnx,rx-pll-selection = <0>;
xlnx,rx-protocol = <1>;
xlnx,rx-refclk-sel = <1>;
xlnx,transceiver-type = <5>;
xlnx,transceiver-width = <2>;
xlnx,tx-buffer-bypass = <1>;
xlnx,tx-no-of-channels = <3>;
xlnx,tx-pll-selection = <6>;
xlnx,tx-protocol = <1>;
xlnx,tx-refclk-sel = <0>;
xlnx,use-gt-ch4-hdmi = <0>;
vphy_lane0: vphy_lane@0 {
#phy-cells = <4>;
};
vphy_lane1: vphy_lane@1 {
#phy-cells = <4>;
};
vphy_lane2: vphy_lane@2 {
#phy-cells = <4>;
};
vphy_lane3: vphy_lane@3 {
#phy-cells = <4>;
};
};
misc_clk_2: misc_clk_2 {
#clock-cells = <0>;
clock-frequency = <100000000>;
compatible = "fixed-clock";
};
refhdmi: refhdmi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <114285000>;
};
zynq_us_ss_0_fmch_axi_iic: i2c@80041000 {
#address-cells = <1>;
#size-cells = <0>;
clock-names = "s_axi_aclk";
clocks = <&zynqmp_clk 74>;
compatible = "xlnx,axi-iic-2.0", "xlnx,xps-iic-2.00.a";
interrupt-names = "iic2intc_irpt";
interrupt-parent = <&gic>;
interrupts = <0 94 4>;
reg = <0x0 0x80041000 0x0 0x1000>;

si5324: clock-generator@68 {
status = "okay";
compatible = "silabs,si5324";
reg = <68>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
clocks = <&refhdmi>;
clock-names = "xtal";
clk0 {
reg = <0>;
clock-frequency = <27000000>;
};

};

dp159: hdmi-retimer@5e {
status = "okay";
compatible = "ti,dp159";
reg = <0x5e>;
#address-cell = <1>;
#size-cells = <0>;
#clock-cells = <0>;
};
};
vcap_hdmi {
compatible = "xlnx,video";
dma-names = "port0";
dmas = <&v_frmbuf_wr_0 0>;
vcap_hdmi_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
vcap_hdmi_port: port@0 {
direction = "input";
reg = <0>;
vcap_hdmi_in: endpoint {
remote-endpoint = <&hdmi_rx_out>;
};
};
};
};
v_drm_dmaengine_drv: drm-dmaengine-drv {
#address-cells = <1>;
#size-cells = <0>;
/* Fill the fields xlnx,vformat based on user requirement */
compatible = "xlnx,pl-disp";
dma-names = "dma0";
dmas = <&v_frmbuf_rd_0 0>;
xlnx,vformat = "YUYV";
dmaengine_port: port@0 {
reg = <0>;
dmaengine_crtc: endpoint {
remote-endpoint = <&hdmi_encoder>;
};
};
};
};


};

 

Thank you everyone.

 

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eliezer
Explorer
Explorer
3,371 Views
Registered: ‎03-21-2019

Why is removing pl.dtsi necessary? Doesn't system-user.dtsi overwrite it anyway?

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systemsdeveloper
Explorer
Explorer
3,366 Views
Registered: ‎06-10-2019

@eliezer  I have just explained both method, you can keep pl.dtsi and overwrites with system-user.dtsi. I was badly seraching for removing pl.dts from build and finally i found it so I have just explained here.

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eliezer
Explorer
Explorer
3,321 Views
Registered: ‎03-21-2019

I see.

 

How did you know how to create the device tree node for the si5324? Is i2c access required?

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