08-01-2019 06:52 PM
I am working with MIPI CSI-2 RX IP. I want to migrate the CSI-2 RX subsystem example design to my ZCU104 FPGA board.
From the schematic of the ZCU104 FPGA board and LI-IMX274MIPI-FMC, the FMC Pins of MIPI are at
MIPIC => F17
MIPID0 => L15
MIPID1 => H18
MIPID2 => E18
MIPID3 => J16
However, when i fix the configuration of the CSI-2 RX subsystem, another two ports are automatically generated.
We can get the information about these new ports in PG232.
It says that these ports must be connected. But PG232 does not mention how to do it. If these ports stay connected, implementation would encount error as follow.
08-01-2019 07:39 PM
You do not need to drive bg*_pin*_nc pins in your RTL design. Leave it as is.
bg*_pin*_nc appears on your IP , because you do not assignment MIPI pins to continuous pins.
Hope this helps
08-01-2019 08:25 PM
Thank you very much for your timely help. If this is not the reason, then how can I fix the error I encountered in implementation? The log was displayed as follow:
08-07-2019 10:15 PM
Hello Ivan @ivanfan
Thank you for your feedback.
1. Critical warnings in the red-box are reproducible.
These critical warnings are produced by MIPI DSI TX. It can be safely ignored. Please expect the fix on Vivado 2019.2 or later.
2. Critical warnings in the green-box are also reproducible.
These critical warnings are produced by HDMI TX IP (since 2018.3 ?!).
Please ignore for now, fix are scheduled in 2019.2 or later.
3. Orange boxes.
Unfortunately I cannot reproduce the issue on my side.
I believe you set incorrect pin assignment on MIPI CSI-2 RX.
Firstly, could you please try use ZCU102 as a project board ?
Please try to generate the MIPI Example Design targeting ZCU102.
After you can confirm that everything are okay. You can change the MIPI D-PHY XDC manually to fit your ZCU104 board connectivity.
The XDC file are something like this:
08-13-2019 02:04 AM
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If this is not solved/answered, please reply in the topic giving more information on your current status.
Thanks and Regards,
08-15-2019 12:10 AM
Thank you so much for your help and detailed answer.
Unfortunately, I only have the zcu104 board on hand, and there is no ZCU102 board. I looked at the block design of the zcu104 base trd and found that the two pins are connected to D16 and L20. I made the corresponding changes in my csi project, and passed the synthesis without errors.
But I encountered another problem while downloading the program. I follow the steps of pg232 to download the program using tcl and get the following results.
I followed the tutorial searched online to modify the psu_init file and still encountered the same problem.
08-19-2019 10:51 PM
Thank you for debugging this.
Yes, have to assigned the bg_pin_nc pins on your device.
Probably this Forum post will helps you on (Mask poll failed at ADDRESS: 0xFD4023E4 MASK: 0x00000010)
Perhaps GTR configuration is not correct.
If this is not helps, suggest you to post a new question in
Thanks & regards
09-03-2019 04:35 PM
Is everything clear for you on this topic?
If your question is answered or your issue is solved, please kindly mark the response which helped find a solution (click on "Accept as solution" button below the reply)
If this is not solved/answered, please reply to the thread giving more information on your current status.
Thanks and Regards,
06-18-2020 06:35 AM
Hi @ivanfan ,
I am also trying to migrate csi2rx design to ZCU 104 and i am facing difficulty for longtime and unlike you I am not getting those two extra pins. Could you please guide me through the steps you have followed?
Please have a look at my query: https://forums.xilinx.com/t5/Embedded-Linux/CSI2-rx-example-for-ZCU104/td-p/1112216
If you need anymore info please let me know. Any help from your side would be appreciated.