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Voyager
Voyager
1,418 Views
Registered: ‎10-21-2015

mipi csi-2 RX operation time limit

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 Hi

I'm using mipi csi-2 rx subsystem ip for mipi camera of Ultra96

It seems to stop ultra96 linux system after it runs about one hour.

Is it normal?

I'm using  180-day evaluation license for it

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Xilinx Employee
Xilinx Employee
1,394 Views
Registered: ‎03-30-2016

Hello @hokim

Yes, it is expected behavior.

1. MIPI CSI-2 RX Subsystem and MIPI CSI-2 TX Subsystem will activated timeout mechanism if evaluation license is used. There is no workaround for this.

2. Re-initialize MIPI IP will not work. You have to power off/on your board or do the FPGA reconfiguration. 
3. The time out duration is dependent on the video_aclk frequency, so time-out duration varies based on video_aclk.
    We cannot give more detail information other than this. :-)
4. If the MIPI CSI-2 Rx Subsystem or  MIPI CSI-2 TX Subsystem has time-out activated, all packets are reported as unsupported data types(ErrID) after time-out
     [ For MIPI CSI-2 RX : which means Interrupt Status Register ISR[8] will get set  Refer PG232]
     [ For MIPI CSI-2 TX : which means Interrupt Status Register ISR[1] will get set  Refer PG260]


Thanks & regards
Leo

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Xilinx Employee
Xilinx Employee
1,395 Views
Registered: ‎03-30-2016

Hello @hokim

Yes, it is expected behavior.

1. MIPI CSI-2 RX Subsystem and MIPI CSI-2 TX Subsystem will activated timeout mechanism if evaluation license is used. There is no workaround for this.

2. Re-initialize MIPI IP will not work. You have to power off/on your board or do the FPGA reconfiguration. 
3. The time out duration is dependent on the video_aclk frequency, so time-out duration varies based on video_aclk.
    We cannot give more detail information other than this. :-)
4. If the MIPI CSI-2 Rx Subsystem or  MIPI CSI-2 TX Subsystem has time-out activated, all packets are reported as unsupported data types(ErrID) after time-out
     [ For MIPI CSI-2 RX : which means Interrupt Status Register ISR[8] will get set  Refer PG232]
     [ For MIPI CSI-2 TX : which means Interrupt Status Register ISR[1] will get set  Refer PG260]


Thanks & regards
Leo

View solution in original post

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Adventurer
Adventurer
1,034 Views
Registered: ‎12-27-2018

Hi,

Can we temporarily disable this time-bomb mechanism or extend for a longer period of time ?

Thanks. 

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Xilinx Employee
Xilinx Employee
1,006 Views
Registered: ‎03-30-2016

Hello @yuko.2828 

You are more than welcome to evaluate any Xilinx IPs using evaluation license. Yes, it will have some time-limit and unfortunately no workaround available for this.

If you find this IP useful for your project, please contact distributor Sales/FAE to get a valid license.
-- Hmm, using 4 pixel per beat with slower video_aclk will extend the time-limit, but reset your board/system is much easier.

Thanks