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Adventurer
Adventurer
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Registered: ‎10-20-2019

mipi csi-2 tx problem

I have a image sensor, it outputs mipi signals to ECU as shown below. I can observe the image from the ECU. Now the ECU did not  recognize the image signal that I transmitted using FPGA. 

2020-05-12_162042.png

I want to confirm the meaning of 'LineCount' parameter of the function 'XCsi2TxSs_SetLineCountForVC'. Is it just the number of active rows? Is the Vertical Blanking or embedded data rows included?

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Adventurer
Adventurer
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Registered: ‎10-20-2019

@karnanl 

This problem is similar to the one that you helped me before. https://forums.xilinx.com/t5/Video-and-Audio/mipi-csi-2-design/td-p/1103338

Now I have checked the signal connection and register dump. They are both ok. When I enabled FE generation option and set the LineCount for VC.,the Line Count Status for VC0 in Interrupt Status Register was always 0x3. 

2020-06-04_142547.png

Look forward to your reply. Thank you!

Best Regards!

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello Wang  @xxwang 

It should be active lines/rows number only. No need to count Vertical blanking lines.
If your RX do not have any requirement on FE-FS interval, you can also try to disable "Register based frame end generation" in the GUI.

Kind regards
Leo

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Adventurer
Adventurer
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Registered: ‎10-20-2019

Hi  @karnanl 

Is there the 'tlast' signal  during the Vertical blanking time?

I am not sure if there is FE-FS interval requirement now.

If I disabled "Register based frame end generation" in the GUI, the ECU  counted  the frame rate reduced  by half. It is strange.

Best Regards!

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @xxwang 

>I am not sure if there is FE-FS interval requirement now.
>If I disabled "Register based frame end generation" in the GUI, the ECU  counted  the frame rate reduced  by half. It is strange.

I have seen similar behavior with some serial/deserializer device.
It seems your ECU has FE-FS interval requirement, that is not defined in MIPI CSI-2 specification.
If FE-FS interval is too close, your ECU does not process the next frame data. 
You need to enable "Register based frame end generation" in the GUI.

 

>Is there the 'tlast' signal  during the Vertical blanking time?

No.


Thanks
Leo

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Adventurer
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Registered: ‎10-20-2019

Hello, @karnanl

Yes, you are right.There are  serializer  and deserializer devices.

I enabled "Register based frame end generation". But I don't know the right number of line count for VC. I have counted the number of 'tlast' signal pulses.  For example, it is 988. Then when I set 988 as the  line count for VC, the Line Count Status for VC0 in Interrupt Status Register was  0x1. When I set 987 as the  line count for VC, the Line Count Status for VC0 in Interrupt Status Register was  0x3.  So I am confused. Why?

Best Regards!

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Adventurer
Adventurer
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Registered: ‎10-20-2019

Hello, @karnanl 

I found some information in the deserializer  datasheet. It may be useless.

2020-06-04_195335.png

Best Regards!

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @xxwang ,

Line_count_reserved.png

I need to check around with internal team to find out the meaning of "Reserved" status here.
Could you please write "0x0000_0300" to register address 0x24, and see if the reserved status remains ?

Kind regards
Leo

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Adventurer
Adventurer
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Registered: ‎10-20-2019

Hello, @karnanl 

OK. Thank you.

Could you please write "0x0000_0300" to register address 0x24, and see if the reserved status remains ?

  I have tried to write both "0x0000_0300"  and "0x0000_0000" ,  the reserved status remained.

2020-06-05_114737.png

Best Regards!

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello

> I have tried to write both "0x0000_0300" and "0x0000_0000" , the reserved status remained.

Thanks for the test. I can see that this register status is persistent.

> For example, it is 988. Then when I set 988 as the line count for VC, the Line Count Status for VC0 in Interrupt Status Register was 0x1.
>When I set 987 as the line count for VC, the Line Count Status for VC0 in Interrupt Status Register was 0x3.

Okay, I need to find out the meaning of reserved in this case.
BTW, May I know the video data format that your sensor is sending ? ( the same data that you are sending to MIPI CSI-2 TX ? )
     Resolution ?
     Frame-rate ?
     Data Type ?
     VC usage ? VC0 only, or VC1/VC2/VC3 are used also?
     Is there anyUser-defined data types in the stream ?

Kind regards
Leo

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Adventurer
Adventurer
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Registered: ‎10-20-2019

Hello, @karnanl 

BTW, May I know the video data format that your sensor is sending ? ( the same data that you are sending to MIPI CSI-2 TX ? )

Yes, the same data. I received snesor's video data using mipi rx ip and connected the AXI-S signal to the mipi tx ip.
     Resolution ?

I am not sure. I am told that it may be 1820×940. The Word Count is 0xAB0=2736, the corresponding number of pixels is 1824(1824=2736*8/12).

I  counted the number of 'tlast' signal pulses, it is 988.
     Frame-rate ?

36fps
     Data Type ?

raw 12 bit
     VC usage ? VC0 only, or VC1/VC2/VC3 are used also?

Judging from 'tdest' signal, VC0 only.
     Is there anyUser-defined data types in the stream ?

I am not sure. There may be embedded data.

Best Regards!

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Adventurer
Adventurer
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Registered: ‎10-20-2019

Hello, @karnanl 

I read the registers of mipi rx ip. But I don't understand.

2020-06-08_133348.png

Best Regards! 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello Wang @xxwang 

I am asking internal teams for clarification on "Reserved" status of MIPI CSI-2 TX.
So, please wait,


Regarding the above question.
This is MIPI CSI-2 RX related questions, It would be better if you could create a new thread for different question topic to avoid confusion.

Regarding reg address 0x10
bit [31:16] is a packet counter, it seems that MIPI CSI-2 RX Subsystem is receiving packets from your sensor.

Regarding reg address 0x60
bit [31:16] is a long packet counter, it does not count short packet received from the sensor.
bit [15:0] is a current byte counter (0xAB0) ==2736 byte, which is Word-count from the Long Packet header.

Kind regards
Leo

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Adventurer
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Registered: ‎10-20-2019

Hello, @karnanl 

Thank you for the reply.

I have read the product guide for the description of the registers.  What I don't understand is why the value of packet counter and long packet counter  change. And are they related to the value of the line count for VC set in MIPI CSI-2 TX register?  I don't know the diffrence between the real sensor's mipi signal and  the signal transmitted by ip cores. So I read  the register value of MIPI CSI-2 RX for more information.

Best Regards!

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @xxwang 

Those MIPI CSI-2 RX registers (packet counter and long packet counter) will be incremented, when MIPI CSI-2 RX receives a new HS packet from sensor.
Since, you are seeing those counter is incrementing (with no other ISR register asserted), it means MIPI CSI-2 RX is working without any issue.

Regards
Leo

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @xxwang 

It seems that you did not do the test correctly.
You should write "0x0000_0300" instead of "0x0000_0030"
     Wang_test_is_not_accurate.png

Could you please re-do the test ?
Please write "0x0000_0300" to register address 0x24, and please let us know if the "Reserved" status is still persist.

Regards
Leo

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Adventurer
Adventurer
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Registered: ‎10-20-2019

Hello, @karnanl 

I am sorry. I am so careless.

The "Reserved" status is still persist.

2020-06-08_193149.png

2020-06-08_193223.png

Best Regards!

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello Wang @xxwang 

Thank you for the test.

From this result, we believe that your sensor might sending a variable line number per-frame.
Sometimes the line-rate per-frame is more than 987 , sometimes less than 987, so both bit[0] and bit[1] are asserted.
a_variable_line_rate_sensor.png

Could you please confirm if your sensor is sending a variable resolution per-frame ?
# You was told that sensor is sending 1820×940,
   How do you calculate the tlast number per-frame ? Did you implemented a counter in your design ?
   Does the counter result reset after Frame-Start ?

Kind regards
Leo

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Adventurer
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Registered: ‎10-20-2019

Hello, @karnanl 

When I set the value of the line count for VC as 2, the "Reserved" status is still persist.

2020-06-09_144507.png

When I set the value of the line count for VC as 1,  the Line Count Status for VC0 in Interrupt Status Register was  0x2. 

2020-06-09_144602.png

Yes, I implemented a counter in my design. The counter result reset after Frame-Start.

I attached some ila files about  the tlast number.  The line_count is the counter of the tlast pulses. We can see the number of tlast pulses between every two 'SOF' pulses is always '0x3dc=988'.

Best Regards!

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Adventurer
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Registered: ‎10-20-2019

Hello, @karnanl 

ADD the attachment.

When I set the value of the line count for VC as 2, the "Reserved" status is still persist.

2020-06-09_144507.png

When I set the value of the line count for VC as 1,  the Line Count Status for VC0 in Interrupt Status Register was  0x2. 

2020-06-09_144602.png

Yes, I implemented a counter in my design. The counter result reset after Frame-Start.

I attached some ila files about  the tlast number.  The line_count is the counter of the tlast pulses. We can see the number of tlast pulses between every two 'SOF' pulses is always '0x3dc=988'.

Best Regards!

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

# edited signal name.

Hello @xxwang 

Thank you for sharing ILA waveform. I can confirmed that tlast counter is always 988.
But, your test result on "VC0 Line-count" is rather confusing.

1. Without any clearing of interrupt register , ideally we should see 0x2 -> 0x3 transition in ISR bit[9:8]
   ( Not as you have reported that ISR bit[9:8] is changing from 0x3 -> 0x2, without clearing the bits. This is not an expected result )

2. Proposal:
   Would you able tp probe the following 2 bits in the ILA:
         *inst.mipi_csi2_tx_ctrl_0.inst.reg_blk.isr_i[9:8]

          *inst.mipi_csi2_tx_ctrl_0.inst.img_iface.genblk2.u_mipi_csi2_tx_ctrl_v1_0_4_axis_iface.line_cntr_vc0_r[15:0]

 


   Our expectation is that signal should reflect ISR bit[9:8] state correctly.
   Please let me know your observation on these signals , when you run MIPI CSI-2 TX.

    For example if you set "VC0 Line-count=987" , do you see ILA waveform assert isr_i[9:8]=0x2 ?
    If this is the case , please try to clear the register, after setting the new line-count.
    Please let me know if you still see the same behavior.

3. Question :
    If you set "VC0 Line-count=988" , did you see any image issue on your ECU ? Is the image received as expected ?

Kind regards
Leo

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Adventurer
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Registered: ‎10-20-2019

Hello, @karnanl 

1.I powered off the board and ECU after each test run. I tested diffrent values of  "VC0 Line-count"  separately.

2.I'd like to probe the ISR bit[9:8]. But I do not know how to do it. Could you give me some guide and help? I do not know where to connect ILA ip core.

2020-06-10_155553.png2020-06-10_155624.png

3.Yes, I saw some image issues on the ECU, I will give you a private message.  I think the image was not received as expected.

Best Regards!

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016


Hello @xxwang 

Pardon me, I just discused with our internal team , they suggested to probe the following three signals instead.

  1. inst/mipi_csi2_tx_ctrl_0/inst/reg_blk/isr_i[9:8]
  2. mipi_csi2_tx_ctrl_0/inst/img_iface/genblk2/u_mipi_csi2_tx_ctrl_v1_0_4_axis_iface/line_cntr_vc0_r_reg[15:0]
  3. mipi_csi2_tx_ctrl_0/inst/img_iface/genblk2/u_mipi_csi2_tx_ctrl_v1_0_4_axis_iface/line_cntr_status_vc0_r[1:0]*

Please keep the trigger on “*.line_cntr_status_vc0_r” with value 0x3, to see if ISR[9:8] is set as 0x3.
The test procedure you have mentioned in (1) is good. Please do not clear any ISR register during the test.

>3.Yes, I saw some image issues on the ECU, I will give you a private message. I think the image was not received as expected.

Hmm, unfortunately I will not be able to understand these ECU error messages.
Please contact your ECO vendor for some helps/hints.

>2.I'd like to probe the ISR bit[9:8]. But I do not know how to do it. Could you give me some guide and help? I do not know where to connect ILA ip core.

You can try the following flow :
(a) Synthesis your design.
(b) Open Synthesized Design
(c) On the "Device" view, right-click and select "Find ..."
     FIND_VIVADO.png
(d) Please search for three nets/signals in your design. (one-by-one)
  FIND_SEARCH_FOR_NET.png

(e) On the "Find Results" tab, please select the signals. Right-click and click "Mark Debug" to add this to ILA signal list.
     ( you need to repeat step (d)(e) three times )

  FIND_RESULT.png

  STATUS_SIGNAL.png

(f) Then you can proceed to the usual "Set up Debug" flow.

   ILA_FLOW.png
    # Please try this flow, and let me know if this is not clear for you.


Question:
You have mentioned that tlast counter result for every-frame is always 988.
Is this TLAST signal captured at the AXI4-Stream interface of MIPI CSI-2 TX ?
Does your counter count TLAST=1 when TREADY=1 ? ( Does your counter consider TREADY=1 state when incrementing TLAST counter ? )
Could you please clarify ?

Regards
Leo

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Adventurer
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Hello, @karnanl 

Thank you for your reply and your detailed instructions.

The ILA files are attached. When I set the value of the line count for VC as 2, I got the ila files in the folder named 'ILA2' . When I set the value of the line count for VC as 988, I got the ila files in the folder named 'ILA988' .

 Question:
You have mentioned that tlast counter result for every-frame is always 988.
Is this TLAST signal captured at the AXI4-Stream interface of MIPI CSI-2 TX ?
Does your counter count TLAST=1 when TREADY=1 ? ( Does your counter consider TREADY=1 state when incrementing TLAST counter ? )
Could you please clarify ?

I captured the tlast signal at  AXI4-Stream interface of MIPI CSI-2 RX in another project that the MIPI CSI-2 RX and the MIPI CSI-2 TX were not be connected.

Best Regards!

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @xxwang 

Thank you for taking all these ILA waveforms. Let us confirm all of these files.
Hmm, In a glance, it seems that MIPI CSI-2 TX is working as expected ..... . We will give you feedback on this.

>I captured the tlast signal at AXI4-Stream interface of MIPI CSI-2 RX in another project that the MIPI CSI-2 RX and the MIPI CSI-2 TX were not be connected.

I see, you mean that MIPI CSI-2 RX TREADY was set as a constant "1", so your tlast counter result should be correct.

Kind regards
Leo

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Xilinx Employee
Xilinx Employee
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Hello @xxwang 

Thank you for sharing your ILA waveforms. I believe/assume that you did not clear ISR during your test.

According to the waveforms, it seems that your sensors is sending frames with different line numbers.
We can see one frame with 1 line and other frame with 988 lines.
Could you please confirm your sensor vendor on this ?

 

1. From register11.wcfg
   We can see line count 0x1 couple of time (first frame ends with 1 line only, next frame ends with 988 lines – actual RAW12 data ).
   reg11.jpg
2. From register01.wcfg
   When you programmed line count = 2.
   Because of earlier one frame – one line packet (user-defined packet?) , ISR[8] is set as 0x1.
   And next frame (In actual 988 lines case), when it crosses line 2, ISR[9] is asserted. So you are seeing the result as ISR[9:8]=0x3.

   reg01.jpg

   I hope you can understand my explanation above.

Unfortunately, if you enabled "Register Based Frame end Generation", line number per-frame must be constant.
Currently your sensor is sending different frame resolution for VC0. This is not supported use-case.
So, one proposal from us is:
Please contact your sensor vendor, check with them if you can change VC setting for your data. For example :
        Sending RAW12 data (with 988 lines per-frame) on VC0
        Sending *** data (with 1 lines per-frame) on VC1

If your sensor can do this, You can set VC0 line-count as 988, and VC1 line-count as 1.

Thanks & regards
Leo

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Adventurer
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Hello, @karnanl 

Thank you for your explanation. 

There's one thing I don't understand.

I probed the SOF signal (tuser[0]). Why did  line_cntr_vc0_r_reg  return to zero while SOF was keeping low?

2020-06-15_140001.png

The ila files are attached.

Best Regards!

 

 

 

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Xilinx Employee
Xilinx Employee
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Hello @xxwang 

Hmm, I do not have the answer for now.
Would you please add the following highlighted signals in your ILA ? ( all of them are MIPI CSI-2 RX outputs )
I want to understand what kind of data that your sensor is sending.

SIGNAL_LIST_for_Wang.png

Kind regards
Leo

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Hello, @karnanl 

The ILA files including the highlighted signals  are attached.

Best Regards!

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @xxwang 

Thank you for sharing your ILA data.
I do not see anything wrong in ILA waveform right now, but we will need additional signals to find out why MIPI CSI-2 TX behave like this. (see below)

something_to_note_from_wang_ila.png


1. I forgot to ask what Vivado version you are using,
   If you are using Vivado 2019.2, please apply the following patch first.
              https://www.xilinx.com/support/answers/73100.html

2. Would you please add the following TX signals on your ILA waveform ?

MIPI CSI-2 TX AXI4-stream signals :
- tuser[0]
- tvalid
- tlast
- tready

MIPI CSI-2 TX internal signals :
- fs_fe_vc0_en_r
- ls_le_en_r
- fe_frm_cntr_vc0_r0   (try to search for the netlist , you may not find the exact netlist name )

Kind regards
Leo

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