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Registered: ‎03-19-2017

mipi csi2-rx subsystem could not output video stream data for Vivado2018.3 on customer board?

Dear,

I had a mipi rx project (one sensor input by mipi rx-csi2 subsystem and display output to display port.) which work fine on ZCU102 board. Now I need to transfer this project into new customer board (xczu15eg different part), but the video output port of mipi csi2-rx subsystem could not output any correct signal ?

I had tried to trace the signals by ila modlue, I found that the video_out_tvaild is always low (video_out_ready is high) but the rxbyteclkhs could detect clock signal?

My setting is as: 

1. one lane 1920x1080 raw10 sensor.

2. lite_aclk=50MHz, video_aclk=150MHz, dphy_clk_200M=200MHz.

I want to ask that 

1. rxbyteclkhs could detect clock signal => Does it indicate that mipi csi2-rx subsystem has already receiving correctly input mipi differental clk signal? If it is, why the video_out could not send correct data output? ( the setting of lite_aclk=50MHz, video_aclk=150MHz, dphy_clk_200M=200MHz.by this sensor had been verified  on ZCU102 board before.)

2. How do I debug this condition? Thank you.

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello p.ching.kuang@gmail.com 

Okay, so your MIPI CSI-2 RX design works on ZCU102 board, but the same design does not work on customer board.

1. Are you using similar system ?
   ( Same FPGA, same sensor, same configuration, only board type is different ? ) (Any difference between both system ?)
2. Could you share MIPI CSI-2 RX + MIPI D-PHY RX all registers dump ?
   # Please check Core Status Register (0x10) bit[31:16]. Is Packet count increasing ?
   # Please check Interrupt Status Register (0x24). Any error bit asserted ?
3. Could you please double check if MIPI CSI-2 RX input pins are assigned correctly ?


Kind regards
Leo


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463 Views
Registered: ‎03-19-2017

1.Different FPGA board only (customer board 's body is xczu15egxxxx type), same sensor, configuration).

2 & 3. Wait for my dump the registers.

How about the issue of "rxbyteclkhs could detect clock signal => Does it indicate that mipi csi2-rx subsystem has already receiving correctly input mipi differental clk signal?" ? 

Would you teach me first, thank you.

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Registered: ‎03-19-2017

Dear,

Should I enable the HS/ESC timeout counters/registers first if I want to dump Core Status Register ?

In previous, I only setup mipi module by GUI only and did not dump the core register before. 

Would you teach me how to do that? Or below SDK code is correct or not ?

#include "xcsiss.h"
XCsiSs CsiSsInst;

//
XCsiSs_Config *ConfigPtr = XCsiSs_LookupConfig(XPAR_CSI_0_DEVICE_ID);
XCsiSs_CfgInitialize(&CsiSsInst, ConfigPtr, ConfigPtr->BaseAddr);
XCsi_ReadReg(CsiSsInst.Config.BaseAddr, 0x10);

XCsi_ReadReg(CsiSsInst.Config.BaseAddr, 0x24);

 

mipi_setting.jpg
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453 Views
Registered: ‎03-19-2017

Sorry, my sensor is one data lane only. By the attached core register figure, I should only dump the Interrupt Status Register 0x1C, not you mention 0x24. Is it right?

csi_core_register.jpg
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383 Views
Registered: ‎03-19-2017

Dear,

I had dump all registers as below:

On ZCU102 board (w/ correct image output)

XCSI_CCR_OFFSET [0x00]=0x1
XCSI_PCR_OFFSET [0x04]=0x0
XCSI_CSR_OFFSET [0x10]=0x9160000
XCSI_GIER_OFFSET[0x20]=0x1
XCSI_ISR_OFFSET[0x24]=0x80060000
XCSI_IER_OFFSET[0x28]=0x0
XCSI_SPKTR_OFFSET[0x30]=0x0
XCSI_VCX_FE_OFFSET[0x34]=0x0
XCSI_CLKINFR_OFFSET[0x3c]=0x0
XCSI_L0INFR_OFFSET[0x40]=0x20
XCSI_L1INFR_OFFSET[0x44]=0x0
XCSI_L2INFR_OFFSET[0x48]=0x0
XCSI_L3INFR_OFFSET[0x4c]=0x0

XCSI_CCR_OFFSET [0x00]=0x1
XCSI_PCR_OFFSET [0x04]=0x0
XCSI_CSR_OFFSET [0x10]=0xd600000
XCSI_GIER_OFFSET[0x20]=0x1
XCSI_ISR_OFFSET[0x24]=0x80060000
XCSI_IER_OFFSET[0x28]=0x0
XCSI_SPKTR_OFFSET[0x30]=0x0
XCSI_VCX_FE_OFFSET[0x34]=0x0
XCSI_CLKINFR_OFFSET[0x3c]=0x0
XCSI_L0INFR_OFFSET[0x40]=0x0
XCSI_L1INFR_OFFSET[0x44]=0x0
XCSI_L2INFR_OFFSET[0x48]=0x0
XCSI_L3INFR_OFFSET[0x4c]=0x0

XCSI_CCR_OFFSET [0x00]=0x1
XCSI_PCR_OFFSET [0x04]=0x0
XCSI_CSR_OFFSET [0x10]=0x11a70000
XCSI_GIER_OFFSET[0x20]=0x1
XCSI_ISR_OFFSET[0x24]=0x80060000
XCSI_IER_OFFSET[0x28]=0x0
XCSI_SPKTR_OFFSET[0x30]=0x0
XCSI_VCX_FE_OFFSET[0x34]=0x0
XCSI_CLKINFR_OFFSET[0x3c]=0x0
XCSI_L0INFR_OFFSET[0x40]=0x0
XCSI_L1INFR_OFFSET[0x44]=0x0
XCSI_L2INFR_OFFSET[0x48]=0x0
XCSI_L3INFR_OFFSET[0x4c]=0x0

...

On customer board (w/o any image output) as below, the ISR register had "0x20000 Detect Stop State", without any error and without "0x80000000 Frame Received" ? Any other suggestion ?

XCSI_CCR_OFFSET [0x00]=0x1
XCSI_PCR_OFFSET [0x04]=0x0
XCSI_CSR_OFFSET [0x10]=0x0
XCSI_GIER_OFFSET[0x20]=0x1
XCSI_ISR_OFFSET[0x24]=0x20000
XCSI_IER_OFFSET[0x28]=0x0
XCSI_SPKTR_OFFSET[0x30]=0x0
XCSI_VCX_FE_OFFSET[0x34]=0x0
XCSI_CLKINFR_OFFSET[0x3c]=0x0
XCSI_L0INFR_OFFSET[0x40]=0x20
XCSI_L1INFR_OFFSET[0x44]=0x0
XCSI_L2INFR_OFFSET[0x48]=0x0
XCSI_L3INFR_OFFSET[0x4c]=0x0

 

XCSI_CCR_OFFSET [0x00]=0x1
XCSI_PCR_OFFSET [0x04]=0x0
XCSI_CSR_OFFSET [0x10]=0x0
XCSI_GIER_OFFSET[0x20]=0x1
XCSI_ISR_OFFSET[0x24]=0x20000
XCSI_IER_OFFSET[0x28]=0x0
XCSI_SPKTR_OFFSET[0x30]=0x0
XCSI_VCX_FE_OFFSET[0x34]=0x0
XCSI_CLKINFR_OFFSET[0x3c]=0x0
XCSI_L0INFR_OFFSET[0x40]=0x20
XCSI_L1INFR_OFFSET[0x44]=0x0
XCSI_L2INFR_OFFSET[0x48]=0x0
XCSI_L3INFR_OFFSET[0x4c]=0x0

...

 

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383 Views
Registered: ‎03-19-2017

For the answer of "3. Could you please double check if MIPI CSI-2 RX input pins are assigned correctly ?"

I had tried to create new project to make all mipi pins to connect ila module (w/o mipi csi2-rx subsystem) and set contraint as below for checking whether the assigned is correctly or not. The waveform result is all have signals detected.

set_property IOSTANDARD HSUL_12 [get_ports {mipi_phy_if_0_clk_p}]
set_property IOSTANDARD HSUL_12 [get_ports {mipi_phy_if_0_clk_n}]
set_property IOSTANDARD HSUL_12 [get_ports {mipi_phy_if_0_data_p[0]}]
set_property IOSTANDARD HSUL_12 [get_ports {mipi_phy_if_0_data_n[0]}]

 

 

 

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355 Views
Registered: ‎03-19-2017

Dear,

For the customer board, the output result of XCSI_L0INFR_OFFSET[0x40]=0x20  is always equal to be 0x20, this is the issue point? If it is, how do I fixed it?

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karnanl
Xilinx Employee
Xilinx Employee
350 Views
Registered: ‎03-30-2016

Hello p.ching.kuang@gmail.com 

>1.Different FPGA board only (customer board 's body is xczu15egxxxx type), same sensor, configuration).

Well noted.

>How about the issue of "rxbyteclkhs could detect clock signal => Does it indicate that mipi csi2-rx subsystem has already receiving correctly input mipi differental clk signal?" ?

Perhaps, yes.
But you need to check CL_STATUS Register of MIPI D-PHY (sub-core).
CL_STATUS_REG.png

Please ensure that INIT_DONE is high, and MODE (bit[1:0]) is 2'b01.


But first I would suggest to read all registers value of MIPI CSI-2 RX Subsystem.
Especially we need to check the following registers
  - Interrupt Status Register (0x24)
  - Core Status Register (0x10)
  - Protocol Configuration Register (0x04)

>Should I enable the HS/ESC timeout counters/registers first if I want to dump Core Status Register ?

No need.
You should be fine using the default HS/ESC timeout value.

>I had dump all registers as below:

Thank you for sharing MIPI CSI-2 RX registers.
please notice that Packt Counter is stay "0", this mean that MIPI CSI-2 RX on your customer board cannot receive any signal correctly.


>set_property IOSTANDARD HSUL_12 [get_ports {mipi_phy_if_0_clk_p}]
>set_property IOSTANDARD HSUL_12 [get_ports {mipi_phy_if_0_clk_n}]
>set_property IOSTANDARD HSUL_12 [get_ports {mipi_phy_if_0_data_p[0]}]
>set_property IOSTANDARD HSUL_12 [get_ports {mipi_phy_if_0_data_n[0]}]

Those pin assignment constraint are not correct. Please fix.
For MIPI CSI-2 RX clock/data lanes, IO should be set as MIPI_DPHY_DCI not HSUL_12.
For a detail example please refer to PG232 Example design.

Kind regards
Leo


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261 Views
Registered: ‎03-19-2017

Dear,

For the issue of "HSUL_12 & MIPI_DPHY_DCI ", I just want to check whether the HW mipi pins connected is fine or not, so I create another test example and make all mipi input pins to be single end HSUL_12 level.

For the formal example of "MIPI CSI-2 RX subsystem", I do not assign any mipi constraint in *.xdc file. The GUI of MIPI CSI-2 RX subsystem will do it for me.

 

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Registered: ‎03-19-2017

Dear,

For the purpose to debug our customer board, I create new design by MIPI DPHY module (as attached schematic and waveform result). I found that the signal rxbyteclkhs, dl0_stopstate and all error signals seem also correct except the dl0_rxdatahs without any data?

Any suggestion how to debug? Please help, thank you.

dphy_schematic.jpg
dphy_waveform.jpg
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karnanl
Xilinx Employee
Xilinx Employee
219 Views
Registered: ‎03-30-2016

Hello p.ching.kuang@gmail.com 

You cannot set a fix value to forcerxmode input port, MIPI D-PHY RX will not work. This is expected result.

Why you are testing with MIPI D-PHY IP ? when your design is using MIPI CSI-2 RX Subsystem ?

Kind regards
Leo


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Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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202 Views
Registered: ‎03-19-2017

thanks for reply.

I just want to capture the waveform of ppi signals for checking what's going on on mipi pins.

How do I setup the forcerxmode pin?

karnanl
Xilinx Employee
Xilinx Employee
182 Views
Registered: ‎03-30-2016

Hello p.ching.kuang@gmail.com 

Do not assert this signal when sensor (TX) is sending HS data.
Please assert FORCERXMODE when TX is sending LP-11, and de-assert this signal after T_INIT period.

MIPI_DPHY_forcerxmode.png

MIPI_DPHY_spec_forcerxmode.png


MIPI D-PHY RX IP has T_INIT is set as 100us, by default GUI setting.
Default_INIT_VAL.png


Kind regards
Leo


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If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
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