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Adventurer
Adventurer
589 Views
Registered: ‎09-03-2015

mipi d-phy initialization problem

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Hy guys,

for our csi2 reception, we are using an IP core with the Xilinx mipi d-phy IP included on an ultrascale zynq device.
We have tested several csi2 sources and all are working except one.
Now we must find out whats wrong with the not working source.
We mesured the Clock and the Data Lanes with an oscilloscope and they are looking good.
The init_done pin of the dphy is always 0.

The MIPI D-Phy Specification says:

"After power-up, the Slave side Phy shall be initialized when Master Phy drives a Stop State (LP-11)
for a period longer than T_INIT"

The Xilinx Doku says:

"T_INIT is considered a protocol-dependent parameter wich must be longer than 100us"

We have also measured the init periods of the clok and the data lanes.

The data lanes period time is about 20ms.

But the clk init period is about 10us. (see picutre)

 

Is that the reason, why we don't pass the initialization phase of the xilinx mipi dphy IP core?
According to our customer, it is not possible to change the T_INIT Time on his side. So, is there any way to solve this problem on our side?


We haven't had this problem in the past because we have used an external dphy outside the FPGA. Maybe the T_INIT time was not important for this chip. So why is it so important for the Xilinx D-phy?

 

Thank you for your help

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Xilinx Employee
Xilinx Employee
555 Views
Registered: ‎03-30-2016

Hello @astei87 

>But the clk init period is about 10us. (see picutre)

Yes, this is the root-cause.
If you cannot modify the sensor setting, please try to modify the INIT register (0x8 offset) from the default 100 us (32'h186A0) to some value shorter than 10us.

Please let us know the result.

>So why is it so important for the Xilinx D-phy?

D-PHY spec mentioned that minimum of 100us is required for initialization.
It seems that your sensor does not meet this requirement.

Regards
Leo

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Xilinx Employee
Xilinx Employee
556 Views
Registered: ‎03-30-2016

Hello @astei87 

>But the clk init period is about 10us. (see picutre)

Yes, this is the root-cause.
If you cannot modify the sensor setting, please try to modify the INIT register (0x8 offset) from the default 100 us (32'h186A0) to some value shorter than 10us.

Please let us know the result.

>So why is it so important for the Xilinx D-phy?

D-PHY spec mentioned that minimum of 100us is required for initialization.
It seems that your sensor does not meet this requirement.

Regards
Leo

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Adventurer
Adventurer
461 Views
Registered: ‎09-03-2015

@karnanl:

thank you very much for your advice. I set the Value to 5 and it works.

We haven't noticed a Register Space there. We haven't activated the AXI interface in the Core also.

But now i am a little bit confused about the value. You said the default Value is 100us. We also read out the 100000 (32'h186A0) from register 0x8 offset.

init_value.PNG

The Dafault Value field sais 100ms. I assumed a write error because 100us should be right.

So for our case i have to set a value lower 10us. I tried to set h1388 (5000) for 5 us. But this value doesn't work.

If i try to set 10 or lower, it works. Now i'm confused because in my understanding i have to set a value in "ns" and not in "us".

I hope i expressed myself clearly.

 

thank you

 

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Xilinx Employee
Xilinx Employee
448 Views
Registered: ‎03-30-2016

Hello @astei87 

Thank you for sharing the result.

>The Dafault Value field sais 100ms. I assumed a write error because 100us should be right.

Yes your understanding is correct, but this typo is already fixed in PG202

The latest PG202 looks like this:

PG202_LATEST.jpg

Regards
Leo