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Observer
Observer
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Registered: ‎02-27-2019

mipi dphy of the FPGA

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I want use the KU series FPGA to do my MIPI-DPHY design. And I have read the “ XAPP1329 Implementing 2.5G MIPI D-PHY Controllers “. My question is, dose the KU only support the unidirection on LP & HS of lane0 ? Does the VUP can natively support D-PHY without the resistor networks or FET ? And does the VUP can support the bidirection on lane0 with LP and HS ?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @liujayne 

UltraScale devices does not support Xilinx MIPI IP. (All MIPI IPs generated from Vivado)
I would suggest to use UltraScale+ Kintex or UltraScale+ MPSoC since these devices have IO with MIPI D-PHY native support and support for 2500Mbps data-rate.

Thanks & regards
Leo

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Adventurer
Adventurer
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Registered: ‎12-27-2018

Hi

VUP only support 1,5Gbps, see the latest datasheet.

2019.1.1 Vivado IP support 2,5Gbps MIPI using KUP.

 

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Observer
Observer
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Registered: ‎02-27-2019

Thank you very much.

May you give me more information about my question.

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @liujayne 

Both XAPP1339 and the MIPI D-PHI IP (using IOs) will only support unidirection for the data and clock lanes.

Yes, on Ultrascale+ devices, the IOs have a D-PHY termination and thus do not need the external resistor networks or FET  as per xapp894. But with that said, as mentioned by @yuko.2828 , 2500Mb/s is only on ZUp/KUP XC devices. The max you can reach with VUP is 1500Mb/s. Unless you use the GTs as per xapp1339, but then you need the external resistor network


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
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Registered: ‎02-27-2019

Thanks a lot.

And I have read the “XAPP894”.

If we should use the bi-direction on the dsi(lane0_LP), do I have to do the schematics followed with the next picture ?

And does this picture can be worked ok with 7 series, US, and US+ ?

无标题.jpg

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Moderator
Moderator
446 Views
Registered: ‎11-09-2015

HI @liujayne 

Yes I ges you can follow the picture for bi-direction.

And does this picture can be worked ok with 7 series, US, and US+ ?

Well...no easy to asnwer. te D-phy IP is not supported on US. So you could apply it but you would need to write your own d-phy IP

Then for US+, you are expected to use the MIPI termination. So by default you will not be able to use the xapp894. However, some customers were able to have it working by modifying the synthesized desgin but this is not supported by Xilinx


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Xilinx Employee
Xilinx Employee
421 Views
Registered: ‎03-30-2016

Hello @liujayne 

Just adding my two cents here....

1. XAPP1339 is created to target some customer system
    You may use this XAPP as is, but there is no technical support on this XAPP, since XAPP1339 provided all the files needed to do implementation.
2. Xilinx has an official solution for 2.5 MIPI. (IP that can be generated via Vivado )
    (As mentioned by @florentw  and @yuko.2828  ) Unfortunately you need to use UltraScale+ Kintex or UltraScale+ MPSoC device to use 2.5Gbps.
3.  dose the KU only support the unidirection on LP & HS of lane0 ?
    Xilinx MIPI IP does not support UltraScale devices.
4.  Does the VUP can natively support D-PHY without the resistor networks or FET ?
     Yes
5.   And does the VUP can support the bidirection on lane0 with LP and HS ?
     No. Bi-directional mode is not supported.

Hope this helps.

Thanks & regards
Leo

-- https://www.xilinx.com/support/documentation/application_notes/xapp1339-mipi-dphy.pdf

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Observer
Observer
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Registered: ‎02-27-2019
Thank you very much, everybody. And @ karnanl “ 3. dose the KU only support the unidirection on LP & HS of lane0 ? Xilinx MIPI IP does not support UltraScale devices. “ Does this case is mean the US can’t support the MIPI , Or the US can’t support the bi-direction , Or the US can’t support the MIPI-DPHY-IP source from the Xilinx, and it should be done by ourselves ?
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Xilinx Employee
Xilinx Employee
388 Views
Registered: ‎03-30-2016

Hello @liujayne 

UltraScale devices does not support Xilinx MIPI IP. (All MIPI IPs generated from Vivado)
I would suggest to use UltraScale+ Kintex or UltraScale+ MPSoC since these devices have IO with MIPI D-PHY native support and support for 2500Mbps data-rate.

Thanks & regards
Leo

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