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5,776 Views
Registered: ‎12-26-2007

number of gateway in and out

The number of gateway in and gateway out must be the same in the design ?
because i am using less gateway out (half  the number of gateway in), when i remove the gateway out i am able to generate my design using hardware co-sim
and when i have them with the gateway in i can't generate
 
another question;
how can i manipulate matrices i system generator ?   i am doing so by taking each element of the matrix as a constant and follow it by a gateway in.....is there any other method ?
10x
 
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Xilinx Employee
Xilinx Employee
5,769 Views
Registered: ‎08-02-2007

There shouldn't be a particular ratio for gateway ins : gateway outs to perform hardware co-sim.  How many ports are you using?  If this occurs with different sets of ports, from few to many, I would suggest opening a Xilinx Technical Support Webcase here:
http://support.xilinx.com/support/clearexpress/websupport.htm

Depending on your matrix properties, you can take it in through a Simulink 'From Workspace' source block into a gateway in.  An example would be the following matrix:

test = [
0,4;
1,3;
2,2;
3,1
];

The first column is the discreet sample time, and the second column is the value.  In the properties of the workspace block, I would suggest turning off 'Interpolate data' selecting either 'holding final value' or 'setting to zero' if you would like the exact values in your matrix.


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