There shouldn't be a particular ratio for gateway ins : gateway outs to perform hardware co-sim. How many ports are you using? If this occurs with different sets of ports, from few to many, I would suggest opening a Xilinx Technical Support Webcase here: http://support.xilinx.com/support/clearexpress/websupport.htm
Depending on your matrix properties, you can take it in through a Simulink 'From Workspace' source block into a gateway in. An example would be the following matrix:
test = [ 0,4; 1,3; 2,2; 3,1 ];
The first column is the discreet sample time, and the second column is the value. In the properties of the workspace block, I would suggest turning off 'Interpolate data' selecting either 'holding final value' or 'setting to zero' if you would like the exact values in your matrix.