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Explorer
Explorer
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Registered: ‎06-05-2014

pin connections for CSI-2 TX to external processor

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When using the CSI-2 TX with a Zynq Ultrascale+ and using pins selected within the IP block does there need to be anything between the FPGA and processor or is it a direct connection?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hello @clutch12

Zynq Ultrascale + architecture have I/O that can natively support MIPI D-PHY. So for connecting MIPI compliant devices does not require any external hardware. You can directly connect from MIPI CSI-2 TX to MIPI compliant external devices.

For information on MIPI DPHY check PG202 (v4.1) (Page 8~9)

Regards,
Bhushan

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hello @clutch12

Zynq Ultrascale + architecture have I/O that can natively support MIPI D-PHY. So for connecting MIPI compliant devices does not require any external hardware. You can directly connect from MIPI CSI-2 TX to MIPI compliant external devices.

For information on MIPI DPHY check PG202 (v4.1) (Page 8~9)

Regards,
Bhushan

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Explorer
Explorer
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Registered: ‎06-05-2014

 @bpatil what if I have an Artix part? Can I just use a resistor network such as what Digilent has done on their zybo-z7 between the mipi/lp pins?

page 2 here

https://reference.digilentinc.com/_media/reference/programmable-logic/zybo-z7/zybo_z7_sch-public.pdf?_ga=2.134164681.613427109.1552692445-610023628.1548343916

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hello @clutch12 

Yes, you can use resistor network or Meticom Solution for 7 series FPGA, For more details please check XAPP894

Regards,
Bhushan

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Explorer
Explorer
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Registered: ‎06-05-2014

got it. thanks!

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