12-10-2018 10:14 AM
I am working with z030 series and having a video pipeline whcih includes rgb2ycrcb_v7_1 IP core.
It seems that I cannot read with XRgb2YCrCb_GetActiveSize what I am setting with XRgb2YCrCb_SetActiveSize(Vsize is correctly but Hsize not). Also even settings the ACTIVE_SIZE(offset 0x20) register still does not solve the issue. As a result I cannot read frames, have instead EOF errors.
Has anyone came across this issue with this IP?
12-11-2018 07:41 AM
I have checked the xrgb2ycrcb.c driver but the code for XRgb2YCrCb_GetActiveSize and XRgb2YCrCb_SetActiveSize seems to be correct.
However i can write and read back correctly Hsize but Vsize is always 0, no matter what I write.
I tried setting the Hsize and Vsize directly using Xil_Out32 function for the ACTIVE_SIZE register(offset 0x20) but i still read back Vsize 0 afterwards even though
the value written at that offset is read back correctly.
Any help would be appreciated as I am confident there is an issue with the driver or IP core.
12-12-2018 08:23 AM
There is definitely an issue in rgb2ycrcb 7.1 Xilinx driver:
void XRgb2YCrCb_GetActiveSize(XRgb2YCrCb *InstancePtr, u16 *HSize, u16 *VSize)
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(HSize != NULL);
Xil_AssertVoid(VSize != NULL);
/* Reads Number of Active Pixels per scan line */
*HSize = (u16)(XRgb2YCrCb_ReadReg(InstancePtr->Config.BaseAddress,
/* Reads number of active lines per frame */ /* Always returns Vsize as 0!*/
*VSize = (u16)(XRgb2YCrCb_ReadReg(InstancePtr->Config.BaseAddress,
If somebody from Xilinx reads this post, maybe will take notice and it will be fixed in the future SDK versions.
After correcting the reading/writing of the ACTIVE_SIZE register for rgb2ycrcb core, as I start the video streaming, as soon as rgb2ycrcb core starts processing the frame(STATUS register PROC_STARTED bit) I get a EOL_LATE slave error and EOF bit in STATUS register is never set(rgb2ycrcb never finishes processing the frame).
The video stream input to the rgb2ycrcb core comes from the tpg core. I have the same configuration for the two cores(width, height).
Does anybody know other reason for having EOL_LATE error when streaming from tpg to rgb2ycrcb?
I have attached a snapshot of the design.
12-14-2018 01:20 PM - edited 12-14-2018 01:23 PM
Thank you for the info. I do not know of any plans to update this core or its drivers.
To take a quick stab at the issue that you are seeing, it looks like maybe the active height is still not being set correctly.
Moving forward, my recommendation is to use the VPSS (PG231) which is the replacement for this core as well as others.
12-17-2018 10:13 AM
Thanks for your answer
active height and width are set correctly now, and most importantly are written correctly in the rgb2ycrcb registers.
The issue lies somewhere else but could not figure out until now
i will take that replacement core into consideration.