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Visitor
Visitor
3,484 Views
Registered: ‎07-26-2011

root raised cosine filter not working in system generator

I want to design root raised cosine filter in system generator. My design specs are: Fs = 100 MHz, Cutoff freq = 0.8MHz, rool off factor = 0.5, upsampling factor = 4. i am using virtex2 board. The availble options for design are mac block and fir compiler. With mac block i am using rcosine matlab function to implement the fiilter.The simulation comes out to be correct but real time output does not with either of the design options.What could be the problem?Any other option available for filter design?What points to be considered while implementing filter?

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Xilinx Employee
Xilinx Employee
3,479 Views
Registered: ‎11-28-2007

Are you using the FIR compiler? Can you provide more details on how the real time output does not work? The first thing I would do is checking the impulse response of the HW to see if the outputs match your RRC filter coefficients.

 


@nauman83 wrote:

I want to design root raised cosine filter in system generator. My design specs are: Fs = 100 MHz, Cutoff freq = 0.8MHz, rool off factor = 0.5, upsampling factor = 4. i am using virtex2 board. The availble options for design are mac block and fir compiler. With mac block i am using rcosine matlab function to implement the fiilter.The simulation comes out to be correct but real time output does not with either of the design options.What could be the problem?Any other option available for filter design?What points to be considered while implementing filter?




Cheers,
Jim
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