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BG
Visitor
Visitor
1,151 Views
Registered: ‎04-16-2021

single lvds exit problem

Hi,

I use zynq 7015 clg 485 FPGA.

I want to drive a panel by using  single lvds. But my single lvds design is not working.

How can I run single lvds part. LVDS.PNG

 

 

 

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27 Replies
drjohnsmith
Teacher
Teacher
1,148 Views
Registered: ‎07-09-2009

basically , you need to instantiate a lvds buffer,

    then place that in the package with the XDC file

        and constrain the pins as LVDS,

 

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BG
Visitor
Visitor
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Registered: ‎04-16-2021

My constrain file is

set_property PACKAGE_PIN W12 [get_ports clkout_p]
set_property PACKAGE_PIN R17 [get_ports {dataout_p[0]}]
set_property PACKAGE_PIN AA11 [get_ports {dataout_p[1]}]
set_property PACKAGE_PIN V11 [get_ports {dataout_p[2]}]
set_property PACKAGE_PIN AA12 [get_ports {dataout_p[3]}]

set_property IOSTANDARD LVDS_25 [get_ports {dataout_p[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dataout_p[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dataout_p[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dataout_p[0]}]
set_property IOSTANDARD LVDS_25 [get_ports clkout_p]

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BG
Visitor
Visitor
1,136 Views
Registered: ‎04-16-2021

How can I  instantiate a lvds buffer, ?

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drjohnsmith
Teacher
Teacher
1,108 Views
Registered: ‎07-09-2009

As far as I know

https://www.xilinx.com/support/packagefiles/z7packages/xc7z015clg485pkg.txt

 

pins are in the PL side,

   I'd better pass to some one else this as to how to get signals through,

 

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bruce_karaffa
Scholar
Scholar
1,098 Views
Registered: ‎06-21-2017

In Vivado, go to the tools menu.  Look for Language Templates=> VHDL or verilog => Device Primitive Instantiation => fpgafamily => I/O Components => Output => Differential Buffer (OBUFDS).

watari
Teacher
Teacher
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Registered: ‎06-16-2013

BG
Visitor
Visitor
973 Views
Registered: ‎04-16-2021

Thank you I control that

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BG
Visitor
Visitor
961 Views
Registered: ‎04-16-2021

Dou you Think my design is wrong ?

Clock 65 Mhz and 455 Mhz for lvds block

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watari
Teacher
Teacher
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Registered: ‎06-16-2013

Hi @BG 

 

Since I can't refer your RTL design, I don't know whether your design is fine or not.

However, XAPP585 is helpful for you to implement FPD link Tx even if your design is correct.

 

Hope this helps.

 

Best regards,

BG
Visitor
Visitor
907 Views
Registered: ‎04-16-2021

Hi I use  zynq  xc7z015 clg485ab... FPGA .. In the fpgafamily block there is not zynq family

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BG
Visitor
Visitor
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Registered: ‎04-16-2021

I see ..I arrange this part my code.

OBUFDS
#(
.IOSTANDARD ("LVDS_25")
)
obufds_inst
(
.I (ser_out),
.O (out_p ),
.OB (out_n )
);

 

But I can not get lvds outputs unfortunetey. I am new about FPGA but I did everything suggested

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bruce_karaffa
Scholar
Scholar
856 Views
Registered: ‎06-21-2017

Some basic questions.  When you say you cannot get LVDS outputs, are you looking at them with a scope?  Is the scope fast enough to see the signals?  Are the LVDS signals terminated when you are looking at them?  Are these signals terminated on the panel you are using?  What kind of connector and cable is used to connect the FPGA board with the panel?  Does the panel respond at all to your signals?  Do you have timing constraints?  Does the design meet them?  And since @drjohnsmith hasn't asked yet, have you simulated?

BG
Visitor
Visitor
848 Views
Registered: ‎04-16-2021

I get outputs from LVDS_dataline_organizer ıp. I checked by using ILA.

outputs of LVD_S4x2_group ip can not connected to ILA port. There is a error.

I control outputs of LVD_S4x2_group ip from outputs of LVDS pins on the card. Pins don't have any output signals.

I use single LVDS cable. Nothing appears on the panel.. My panel clock is 65 mhz that is in the panel data sheet.

I give 65 mhz clock for CLKDIV and 65x7=455 Mhz clock for CLK

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BG
Visitor
Visitor
845 Views
Registered: ‎04-16-2021

 Sorry,

What do you mean about timing constraints?

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watari
Teacher
Teacher
810 Views
Registered: ‎06-16-2013

Hi @BG 

 

> Hi I use  zynq  xc7z015 clg485ab... FPGA .. In the fpgafamily block there is not zynq family

 

As I already shared, fpga fabric is same as 7 series and it's artix-7.

 

So, you can refer what I already mentioned.

 

Hope this helps,

 

Best regards,

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bruce_karaffa
Scholar
Scholar
786 Views
Registered: ‎06-21-2017

Is the bank driving the LVDS signals powered by 2.5V? 

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BG
Visitor
Visitor
784 Views
Registered: ‎04-16-2021

Yes

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BG
Visitor
Visitor
756 Views
Registered: ‎04-16-2021

I get these warnings:

WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_wiz_0/clk_out1(clk) and /lvds_4x2_group_0/clk_par(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_wiz_0/clk_out2(clk) and /lvds_4x2_group_0/clk_ser(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /proc_sys_reset_0/bus_struct_reset(rst) and /lvds_4x2_group_0/rst_io(undef)

 

 

 

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bruce_karaffa
Scholar
Scholar
726 Views
Registered: ‎06-21-2017

I think you need to do two things:

1.  Post your code for the lvds_4x2_group RTL block.

2.  Get an oscilloscope and probe the signals while the panel is connected to see what the lines look like.

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BG
Visitor
Visitor
646 Views
Registered: ‎04-16-2021

.

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BG
Visitor
Visitor
641 Views
Registered: ‎04-16-2021

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08/10/2020 11:20:40 AM
// Design Name:
// Module Name: LVDS_Serdese_IO
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module LVDS_Serdese_IO
(
input wire rst_io ,//
input wire clk_ser,//
input wire clk_par,//
input wire [6:0] pdata ,//
output wire out_p ,//
output wire out_n //
);

wire ser_out;
OSERDESE2
#(
.DATA_RATE_OQ ("SDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (7),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("MASTER")
)
oserdese2_inst
(
.RST (rst_io ),
.OCE ( 1'b1 ),
.CLK (clk_ser ),
.CLKDIV (clk_par ),

.D1 ( pdata[0]),
.D2 ( pdata[1]),
.D3 ( pdata[2]),
.D4 ( pdata[3]),
.D5 ( pdata[4]),
.D6 ( pdata[5]),
.D7 ( pdata[6]),
.D8 ( 1'b0 ),
.OQ (ser_out ),

.TCE ( 1'b0 ),
.T1 ( 1'b0 ),
.T2 ( 1'b0 ),
.T3 ( 1'b0 ),
.T4 ( 1'b0 ),
.TQ ( ),

.OFB ( ),
.TFB ( ),
.TBYTEIN ( 1'b0 ),
.TBYTEOUT ( ),

.SHIFTIN1 ( 1'b0 ),
.SHIFTIN2 ( 1'b0 ),
.SHIFTOUT1 ( ),
.SHIFTOUT2 ( )
);

OBUFDS
#(
.IOSTANDARD ("LVDS_25")


)
obufds_inst
(
.I (ser_out),
.O (out_p ),
.OB (out_n )
);
endmodule

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drjohnsmith
Teacher
Teacher
641 Views
Registered: ‎07-09-2009

My apologies,

I did not realise your using oserdes, 

and 

did you simulate ?

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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BG
Visitor
Visitor
641 Views
Registered: ‎04-16-2021

I controled output signal by using oscilloscope. However there is nothing..

I think I'm missing a fundamental point. 

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BG
Visitor
Visitor
590 Views
Registered: ‎04-16-2021

Sory, I misunderstood. Yes I simulated .

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bruce_karaffa
Scholar
Scholar
364 Views
Registered: ‎06-21-2017

What do you mean "there is nothing"?  What is the average DC voltage on the pins?  Is your scope fast enough to see the signals?  What are the bandwidths of the scope and probes?

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watari
Teacher
Teacher
338 Views
Registered: ‎06-16-2013

Hi @BG 

 

>I think I'm missing a fundamental point.

 

As I already mentioned before, did you refer my suggestion ?

If no, would you implement my suggestion instead of your rtl to investigate the route cause ?

 

Best regards,

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BG
Visitor
Visitor
279 Views
Registered: ‎04-16-2021

Yes, I took your suggestion into clonsideration. 

I work on RTL part of project. 

 

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