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Visitor
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Registered: ‎01-19-2019

tuser is kept more than one cycle in mipi csi-2 rx subsystem

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From the last thread https://forums.xilinx.com/t5/Video/mipi-csi-2-rx-subsystem-only-receive-frames-when-fpga-is-powered/td-p/951571, the CRC and ECC are fixed.

When capturing the data output from the mipi csi-2 rx subsystem, the tuser is kept more than ONE clock cycle, which will corrupt the later IP such as axis_subset_convert. 

wave.jpg

Are there any ideas why the tuser is kept more than 1 clock cycle?

 

Thank you for your time and any help is appreciated.

Regards,

Chunjie

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Moderator
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Registered: ‎11-09-2015

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

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Hi @chunjiew ,

Do you have any updates on this? Is everything clear enough for you?


If your question is answered or your issue is solved, please mark the response which helped as solution (click on the button "Accept as solution" below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Visitor
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Registered: ‎01-19-2019

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

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Hi @karnanl

Could you take some time to check the issue about tuser signal, which is quite strange? I use the evaluation license.

From the register status, as follows, the IP should work well.

mip-reg.png

Your time is quite appreciated.

Thanks,

chunjie

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Contributor
Contributor
1,163 Views
Registered: ‎11-15-2018

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

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Forgot the IP processing path: MIPI CSI-2 RX -> axis_sub_converter -> demosaic -> VDMA. This path is just for debugging. It seems that demosaic cannot handle bad frame, such as the two consecutive tusr.

Your ideas are appreciated.

mipi_process.png

Thanks

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

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Hello @chunjiew 

tuser is a multiple bits signal. ( 96bits for 2018.1 MIPI CSI-2 RX SUbsystem )
Could you please check your RTL connectivity ?


tuser[0] should only "high" for one clock every frame (tuser[0] == Start of Frame).
Please let me know if tuser[0] is behave incorrectly on your system, we will need to do some debugging.

 

Thanks and regards
Leo

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Visitor
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Registered: ‎01-19-2019

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

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Hi @karnanl

 

The issue has been fixed as the later demosaic is not working well, so the stream stops.

 

Thanks again,

Chunjie

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Moderator
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Registered: ‎11-09-2015

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

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HI @chunjiew ,

I do not think we can say that the deinterlacer is not working well. This is an expected behaviour, the deinterlacer expect full frames and is not designed to handle bad frames.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Xilinx Employee
Xilinx Employee
1,086 Views
Registered: ‎03-30-2016

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

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Hello @chunjiew 

  1. tuser is a 96 bits of signal. So if your design only enabled tuser[0] in the GUI,
    Please enabled all of 96 bits and could you please share the ILA with us ?
    by enabling all the bits, we can see all the information such as Data type, word count etc

  2. (a) Did you enable “Embedded non-image interface” in your design ?
    (b) Do you have embedded non-image data coming from your sensors ?
    -- If the answer : (a) No, (b) yes
        then this might occurs depends on sensor data.

  3. One more thing, is your sensor has multiple VC of video stream ?
    If yes , please capture TDEST on ILA too.

 

Thanks & regards
Leo

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Moderator
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Registered: ‎11-09-2015

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

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Hi @chunjiew ,

Do you have any updates on this? Is everything clear enough for you?


If your question is answered or your issue is solved, please mark the response which helped as solution (click on the button "Accept as solution" below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Visitor
Visitor
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Registered: ‎01-19-2019

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

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Hi @karnanl  and @florentw 

 

Sorry for the late replay, and many thanks for your answer. The solution has been accepted.

 

Regards,

Chunjie

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Adventurer
Adventurer
623 Views
Registered: ‎06-05-2019

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

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Hi @chunjiew 

I am a newcomer of FPGA and I am debugging the csi example design. I wonder how to check the status of the registers as you showed in the picture?

Thank you in advance

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Contributor
Contributor
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Registered: ‎11-15-2018

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

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Hi @ivanfan
In the Linux, I use the command devmem to read the registers from MIPI via IIC, and the code looks like:

devmem 0xb0000004
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Newbie
Newbie
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Registered: ‎10-18-2014

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

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I am also observing that the MIPI RX subsystem emits tuser(0) (start of frame) during two AXI stream words rather than one as you would expect.

I am observing this in simulation using a MIPI RX subsystem with 4 data lanes emitting two pixels per clock cycle of RAW12 data.

I thus suspect there is a bug in the MIPI RX subsystem.

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

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HI @okraigher 

Yes this is a known issue which should be fixed in 2019.2.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**