cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Participant
Participant
374 Views
Registered: ‎07-27-2016

uhd-sdi GT

I am configuring a Transceiver Core on ZynqUltrascale+ for (upto 12G) Tx.

I've referred pg289-v-smpte-uhdsdi-tx-ss.pdf and pg380-uhdsdi-gt.pdf.

As mentioned in these documents we provide 148.5 and 148.5/1.001 MHz clocks to the 2 ref-clock ports of the COMMON.

However I miss to find out, how to switch the clock-source for the Transmitter-reference ?

PG380 says txsysclksel selects the TX units serial clock source between the PLLs. But this port is not available.

Thanks,

Any help welcome.

 

 

 

0 Kudos
5 Replies
Highlighted
Xilinx Employee
Xilinx Employee
345 Views
Registered: ‎04-15-2008

The integer vs. fractional frame rate is controlled at a higher level with the "mode" signal (tx_m).  Review PG289 Table 5-2, that should help.

Benoit

**~ Don't forget to reply, give kudos, and accept as solution.~**

Highlighted
Participant
Participant
336 Views
Registered: ‎07-27-2016

Thanks for the reply, 

However, So if the UHD-SDI-GT is to auto select the required PLL for source at configuration it must be given, (i.e QPLL0 = 148.5 QPLL1 = 148.5/1.001 or the other way round)

Is Vivado picking that from the XDC constrain ?

 

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
308 Views
Registered: ‎04-15-2008

The Example Design in Chapter 5 is a passthrough (not a Tx-only as you requested), so the rx_m/rx_rate from Rx is pushed to Tx in that case.  It would help you to generate the passthrough Example Design as a starting point and review the firmware for the A53 processor. 

Please review PG289 (September 15, 2020) Chapter 3, it is seven pages to read.  The section named "CPLL Clocking" is important, I know there have been some changes recently, you can see the expected GT RefClk frequencies and the clock muxing for the GT Tx.  There is an important note on page 32.

The tx_m/tx_rate frame rate is controlled with A53 firmware (register access: if using the Native Video Interface (Table 2-8), the sdi_tx_ctrl[31:0] register, bit 7;  if AXI4-Stream configuration, the MODULE_CTRL register (offset=0x04), bit 7 (see Table 2-13 and Table 2-15 for its description)).

Benoit

**~ Don't forget to reply, give kudos, and accept as solution.~**

Highlighted
Participant
Participant
274 Views
Registered: ‎07-27-2016

Hi @benoitp 
Thanks for you reply,
But I'd like to rephrase my question.
Yes I read the page you mentioned and generated the Example-design. But unfortunately I don't have the eval-board to test this.

I understand the register-offset- 0x4, bit [7] sets the TX_M. This bit is passed on to the UHD-SDI GT as side-band info.

However, once the GT knew the TX_M value, one of the helper module inside UHD-SDI-GT must select the correct PLL to provide ref-clock to Tx-path.
For that to happen we must set the clock-frequency as part of the UHD-SDI-GT configuration.
The only setting available for each Tx link are the actual PLL location,
(i.e QPLL0, QPLL1, and CPLL) also we have option to select What is the source for QPLL0 and QPLL1 (from the neighboring Quads)
There is no explicit frequency-value set for these PLLs. (For DRP clock, we do set this).

This is where my question. How would the UHD-SDI-GT switches to the correct reference-clock without knowing the available frequencies on connected PLLs.

 

Thanks

 

0 Kudos
Highlighted
Moderator
Moderator
253 Views
Registered: ‎04-09-2019

Hello @murali_4i2i ,

Xilinx SDI IP's required a reference clock frequencies of 148.5 Mhz (GT Ref Clk0) for Integer frame rate videos, 148.35Mhz (GT Ref Clk1). These clock frequencies should generate with an external oscillators. we are using Si570 and si5328 on our evolution board to generate these clocks. So, user has to take a call, whether the design should support both integer and fractional frame rates, then user must use both ref clocks (148.5 for RX and 148.35MhZ for TX path) and both has to be fed to the 2 GT ref clock pads. If the design should support only integer frame rates then only 148.5Mhz clock is sufficient for both TX and RX paths. So, user has to take a call for their design, whether they need to provide 148.5 Mhz clock (or) 148.35Mhz clock to the GT.

Since, 148.5Mhz and 148.5Mhz clocks are fixed, based on the data rate captured, The output clocks for SDI RX path and SDI TX paths will generate based on the SDI data mode detected, as addressed in the Table 5-2 of PG290 and PG289. the output clock (rxoutclk, txoutclk) frequencies for integer & non-integer frame rates will define by rx_m or tx_m signal.

Hope the above information provides you the clear picture, regarding your concern.

Kind Regards,

Ashok.