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francocapraro12
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Registered: ‎09-27-2018

uhdsdi_gt_ctrl in Ultrazed -EV SOM in SDI TX

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Hello. Im trying to use the SDI GT IP CORE. Im using a Ultrazed EV SOM+CC .I saw the examples for ZCU106 and it use a "uhdsdi_gt_ctrl.v" to send the signals to cmp_gt_ctrl[63:0].Im just trying to send a Video Pattern Generator to SDI TX. NOT RX

1)Since i dont have a SI5324. How can i port this module to my board ? Right now im trying to do it with a GPIO + sdk code ( I know is not optimal)

francocapraro12_1-1622704762051.png

2) Seeing the uhdsdi_gt_ctrl code, i just need to send a  sentence of "0 , 1, 0 " for cmp_gt_ctrl[0] and after a  "1" to cmp_gt_ctrl[14]?

		XGpio_DiscreteWrite(&led_device, 1, 0x01);
//bit 14 asserted, bit 0  asserted
		XGpio_DiscreteWrite(&gsdi_device, 1, 0x4001);
		xil_printf("2\n\r");
		XGpio_DiscreteWrite(&led_device, 1, 0x02);

//bit 14 asserted, bit 0 not asserted
		XGpio_DiscreteWrite(&gsdi_device, 1, 0x4000);
		xil_printf("3\n\r");
		XGpio_DiscreteWrite(&led_device, 1, 0x03);



Im receiving  a "1" in cmp_gt_sts[9]. All Axis have 0's values:

francocapraro12_3-1622705725706.png

francocapraro12_4-1622705780494.png

 



 

 

 

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francocapraro12
Adventurer
Adventurer
204 Views
Registered: ‎09-27-2018

I could resolve it. I did little changes in the code because it has an errata in 2 definitions( they need to be initialized to 0, because it will never count if we dont start in 0:

 

 

......
reg  [11:0]	qpll0reset_cnt; //WE NEED INITIAL VALUE HERE AND
wire qpll0reset_cnt_tc;
reg  [11:0]	qpll1reset_cnt; // HERE
......
.....

 

TO:

....
reg  [11:0]	qpll0reset_cnt=0;
wire qpll0reset_cnt_tc;
reg  [11:0]	qpll1reset_cnt=0;
....

View solution in original post

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francocapraro12
Adventurer
Adventurer
205 Views
Registered: ‎09-27-2018

I could resolve it. I did little changes in the code because it has an errata in 2 definitions( they need to be initialized to 0, because it will never count if we dont start in 0:

 

 

......
reg  [11:0]	qpll0reset_cnt; //WE NEED INITIAL VALUE HERE AND
wire qpll0reset_cnt_tc;
reg  [11:0]	qpll1reset_cnt; // HERE
......
.....

 

TO:

....
reg  [11:0]	qpll0reset_cnt=0;
wire qpll0reset_cnt_tc;
reg  [11:0]	qpll1reset_cnt=0;
....

View solution in original post

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