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Adventurer
Adventurer
717 Views
Registered: ‎02-04-2017

use xc7k325t's bank118, rx's pin is E4 D6 B6, tx's pin is B2 C4 D2, rx[0]E4->TX[0]B2. tx cannot show

Hello,

 we use xc7k325t's bank118, rx's pin and  tx's pin is follow picture, tx cannot show video, why?

 rx[0]pin E4  ----   TX[0]B2

 rx[1]pin D6  ----   TX[1]C4

 rx[1]pin B6  ----   TX[2]D2

P(UD~BPWR4}@2XQOM]PN5N4.png

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Scholar
Scholar
699 Views
Registered: ‎02-01-2013

 

Usually, RX & TX are used in pairs. Based on your schematic symbol, you've swapped RX & TX for two of the transceivers: RX0 <> TX2 and RX2 <> TX0. RX1<>TX1 looks to be unaffected. Perhaps your video protocol doesn't like this.

-Joe G.

 

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Xilinx Employee
Xilinx Employee
610 Views
Registered: ‎08-02-2007

@autelchengpeng

@jg_bds makes a good point that your TX lines seem to be swapped. Which protocol you are trying to achiever? Can you provide system diagram in your design? Do you see any data from parallel data(link_data) of GT?  It can tell if the issue is related to swapped GT lanes or not.

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Moderator
Moderator
564 Views
Registered: ‎11-09-2015

Hi @autelchengpeng,

Do you have any updates on this? Was the replies from @jg_bds and @xud enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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