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Contributor
Contributor
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Registered: ‎08-09-2020

video phy controller for HDMI

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how to change them into new  values(transcivwe width:2  ,line rate:2.97) ?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@ha4456 

Figure 17 and 18 in Chapter 4 of PG230 shows the initial flow 

xud_0-1598947371264.png

 

xud_1-1598947390798.png

GT TX phase alignment sequence and TX/RX  reset sequence is part of Video PHY initial flow, you can find more information and associated waveform figure in Transceiver User Guide. Different device families have different types of GT.

Register direct access is not supported by HDMI. In Appendix D of PG235/236, it provides more details on API description, and user case examples on what API is needed to initialize the design.

Simulation is not supported either. There is no simulation waveform for Video PHY. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@ha4456 

What's Vivado version,  device family, package type and speed grade? Transceiver width should be changeable.  I need to double check.

The Max line rate is already 5.94G.

It's mentioned in PG230 : 

TX/RX Max GT Line Rate: Specifies the maximum line rate for the transceiver. For HDMI protocol, this option is fixed to 5.94 Gb/s.

 

 

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Contributor
Contributor
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Registered: ‎08-09-2020

vivado2018.3

vu440-2892-1-c

1>is there a 10bit to 40bit convertion bridge for this hdmi phy?

2>how to force this phy to work on 1.485Gbps mode ?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@ha4456 

This has been documented in latest PG230 :

xud_0-1597766366428.png

 

Video PHY driver handles the line rate.Depending on the resolution and color space, driver calculates the needed line rate, access DRP interface of GT, and configure it to the correct line rate.

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Contributor
Contributor
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Registered: ‎08-09-2020

 

how to define a lower clk freq for timing closure?

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@ha4456 

The corresponding reference clock frequencies must be constrained at the Vivado Project top level XDC file at 297 MHz; that is, create_clock -period 3.367[get_ports <HDMI TX/RX REFCLK portname>]

This is the constraint to define the clock freq for Video PHY. Please note for 4kp60, the reference clock frequency is 148.5Mhz, not 594Mhz(pixel clock).

 

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Contributor
Contributor
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Registered: ‎08-09-2020
1> there is a register initial sequence for video phy controller?

2>where to find a simulation waveform for video phy controller? the simulation can't be launched inside vivado.
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Xilinx Employee
Xilinx Employee
146 Views
Registered: ‎08-02-2007

@ha4456 

Figure 17 and 18 in Chapter 4 of PG230 shows the initial flow 

xud_0-1598947371264.png

 

xud_1-1598947390798.png

GT TX phase alignment sequence and TX/RX  reset sequence is part of Video PHY initial flow, you can find more information and associated waveform figure in Transceiver User Guide. Different device families have different types of GT.

Register direct access is not supported by HDMI. In Appendix D of PG235/236, it provides more details on API description, and user case examples on what API is needed to initialize the design.

Simulation is not supported either. There is no simulation waveform for Video PHY. 

View solution in original post

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@ha4456 

If everything is clear, can you mark accept solution and close this thread please?

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