07-14-2020 03:54 AM
HI, is there anyone who can help me to impove the throughput of VPSS?
I am doing some test with video processing subsystem IP, version 2.2,
clock 200MHz， use scaler only mode , 2 pix per clock. The device: ZYNQ xc7z045。
But the output of VPSS is only one clock active in two clock cycles, like the m_axis_0_tvalid signal in the next picture.
07-16-2020 02:07 AM
I am a colleague of sam_166 . I will give more info about this problem.
The scaler is configured 2 samples per clock. Input stream is set to 1920x1080, output stream is set to 3840x2160. s_axis_tvalis is always assert high.
According to our test, this problem is related to the scaler clock frequency. For 7z045-3, when the clock below 180Mhz, data is output every clock , but when the clock set to 200Mhz or higher , data is output every two cycle, although the clock constraint is met.
Is this normal？According to my understanding, if the clock is too high, the tool can report the timing is not satisfied, instead of changing the working mode of IP.
Can anyone help us？ Thanks a lot.
07-18-2020 11:16 PM
Are you using system differential clock or normal clock? What is your frame rate of input and output stream? Can you show VPSS input/output stream configuration report by using "XVprocSs_ReportSubsystemConfig()" function in SDK/VITIS application?
07-27-2020 12:34 AM
You need to take in account the input data. If your input is not fast enough to feed the VPSS then the VPSS will have a sparse output. The VPSS will not guess the input pixel values. So increasing the frequency will not help if the input is not fast enough and the more you increase the frequency the more you will see a sparse data.
Maybe consider adding a VDMA or video frame buffer to be able to buffer multiple frames and repeat them if not fast enough.
09-02-2020 01:56 AM
Do you have any update on this? Is everything clear for you?
09-02-2020 06:43 PM - edited 09-02-2020 06:50 PM
Can you built an test project to verify the problem we feedback ？
The project can be very simple. The VPSS configration is as the picture below :
The scale input stream is set to 1920x1080, output stream is set to 3840x2160. s_axis_tvalis is assert always high.
When clock freq high to 200Mhz for zynq7045-3 , or 300Mhz for ku060-2, the VPSS output will valid every two cycle. But if we lower the clock frequency, for example 150Mhz for zynq7045-3, and 250Mhz for ku060-2, the VPSS output will valid every cycle.
It seems that the clock frequency will affect the synthesize result of the module.
09-23-2020 02:19 AM
The output rate will be linked to your input. The VPSS cannot go faster than what you feed.
If you have a 1920x1080@30Hz input, then your pixel clock might be something like 124MHz. Thus if you run at 150MHz, you might be consuming enough input to produce the output. However, if you increase the frequency, the input might not keep up with the rate thus you might see the output rate not following
11-23-2020 04:28 AM
We are experiencing the same issue, but with 4 pixel per clock and a clock frequency of 150 MHz.
tvalid on input is always high, so this is not related to a slow input:
Yet, output is only valid every other clock cycle.
Note that this same design was working prior to the upgrade to vivado 2020.1
Did you find a solution to this issue?