10-19-2020 08:26 PM
Hi florentw
I have test the project of video series 29 in my board,and I have changed some parameters to fit my board.
As I described before,when I changed the parameter of input/output resolution by uart,the video have changed,the video seems to have shifted to right.
shifted video
I did captured the reset signal of "aresetn_io_axis" from VPSS. When I change the resolution or reinitialize the application,the reset signal did happening and below is the signal.
reset signal from VPSS
AND I had captured the inout video stream signal of vpss and VDMA. I set the test patten mode be red,and the active video coulde be red/blue/green randomly along with the action of resolution changing. I foud the stream data of VDMA is different with VPSS signal .
10-22-2020 02:43 AM
Then I am not sure why the AXI4-Stream to video out is locked if there is a EOL error.
Anyway, at least we have seen that the pipeline was coming from the VDMA internal pipeline.
One other suggestion I have is to connect the VPSS and AXI VDMA (and maybe all the element in the pipe, thus do not use the reset output from the VPSS) to the same reset and apply a reset before changing the resolution
10-20-2020 01:44 AM
This is difficult to comment on the AXI VDMA signals because you are looking at the memory mapped interface. On the memory mapped interface you might have packeted data so I am not surprised this is different from the AXI4-Stream interface.
So I would recommend you only compare the AXI4-Stream interfaces (compare what is comparable).
But here the content is shifted but seems correct. So what I would recommend is that you take captures triggering on the tuser signal.
Then compare the output of the TPG, VPSS and AXI VDMA before and after the resolution change. This way you can see from where the shift is introduced
10-20-2020 11:37 PM
Hi
I have captured the signal of AXI Stream as your suggestion,and below is the corresponding relationship of ILA signal and actual signal.
ILA signal | Actual signal |
slot 1 | TPG out“ m_axis_video ”& VPSS in“ s_axis ” |
slot2 | VPSS out" m_axis ”& VDMA in“ S_AXIS_S2MM ” |
slot0 | VDMA out “ M_AXIS_MMS ” |
I have set the color mode to be "colorbar" and trigger the TUSER falling signal.Below is the screenshot of TPG, VPSS and AXI VDMA stream signal before and after the resolution changing.
trigger slot1 tuser
slot1 before resolution change
slot1 after resolution change
trigger slot2 tuser
slot2 before resolution change
slot2 before resolution change
trigger slot0
slot0 before resolution change
slot0 before resolution change
Comparing the output of the TPG, VPSS and AXI VDMA before and after the resolution change,I found the VDMA out stream"M_AXIS_MMS" changed with resolution change.The TUSER falling signal happend erlier than actual colorbar frame change.
10-21-2020 01:35 AM
Thanks for the ILA captures. I am not sure why this is happening. Maybe some part of the AXI VDMA are not flushed...
Could you do one testing: can you try to do a soft reset of the AXI VDMA S2MM and MM2S interfaces (bit 1 of 0x00 and 0x30)?
10-21-2020 01:43 AM
10-21-2020 02:33 AM
hi
I have test the soft reset of VDMA as your suggest.But I found the soft reset bit was bit2 of 0x00 and 0x30 from PG020.
I set the bit 2 to be 1 of 0x00 and 0x30 before reconfigure VDMA, But the situation has not improved.
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x30, 0x04);
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x00, 0x04);
10-21-2020 04:03 AM
Hi
I have changed the sequence of soft_reset & vpss configure.
When soft_reset happend earlier than vpss configure, the video no longer shift ever,but the status of "axi4-stream to video out " is 0x3B7.
// configure the soft reset of VDMA
vdma_soft_reset();
// configure the VPSS
configure_vpss(periphs_ptr->Vproc_ptr, &periphs_ptr->video_pipe_config.Stream_in,
&periphs_ptr->video_pipe_config.Stream_out);
But when vpss configure happend earlier than soft_reset ,the video will shift with resolution changing.
// configure the VPSS
configure_vpss(periphs_ptr->Vproc_ptr, &periphs_ptr->video_pipe_config.Stream_in,
&periphs_ptr->video_pipe_config.Stream_out);
// configure the soft reset of VDMA
vdma_soft_reset();
So,we should soft_reset the VDMA mm2s & ss2m before reconfigure of VPSS.
But I don't know why, can you explain detailed about this phenomenon.
Thanks.
10-22-2020 01:37 AM
With the soft_reset before the VPSS reconfigure, you are still seeing the output on the screen?
Does the status remain to 0x3B7 after few seconds?
10-22-2020 02:27 AM
Yes
10-22-2020 02:43 AM
Then I am not sure why the AXI4-Stream to video out is locked if there is a EOL error.
Anyway, at least we have seen that the pipeline was coming from the VDMA internal pipeline.
One other suggestion I have is to connect the VPSS and AXI VDMA (and maybe all the element in the pipe, thus do not use the reset output from the VPSS) to the same reset and apply a reset before changing the resolution