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newages00
Visitor
Visitor
8,428 Views
Registered: ‎01-02-2008

why FIR of system gen 9.2 cannot resolved in ISE?

I had synthesized the xilinx simulink design of system generator to generate VHDL by pressing system generator token.
But when generated VHDL is imported into ISE 9.2 it's failed and came out with the error
FIR cannot be resolved in Virtex4.
Why it happen?
Is it any altenative solution?
thanks.


Message Edited by newages00 on 02-17-2008 10:14 PM
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jbass
Xilinx Employee
Xilinx Employee
8,413 Views
Registered: ‎08-02-2007

Are you using the FIR Compiler?
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newages00
Visitor
Visitor
8,403 Views
Registered: ‎01-02-2008

i used xilinx reference blockset n-tap MAC FIR filter.
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jbass
Xilinx Employee
Xilinx Employee
8,399 Views
Registered: ‎08-02-2007

The reference designs are not fully tested for all possible options / architectures (thus the term reference).  If you are planning to implement a FIR filter, I would highly recommend using the FIR Compiler as this would make the best use of the device's architecture.  You can find this in the Xilinx Blockset -> DSP.
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newages00
Visitor
Visitor
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Registered: ‎01-02-2008

ok. thanks.
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