12-17-2019 07:40 AM
Hi,
We are trying to Implement HD-SDI interface in Artix-7 FPGA.
We have gone through the XAPP1097 Application note and trying to simulate the files provided.
But we are stuck as the tx_usrclk stopped as reset is asserted within 5us of run time.
Can anyone suggest what could be the issue ?
12-18-2019 01:16 AM
Hello @anilsutej ,
Most Probably this issue is because of GTP Initialization process. I noticed that in Your waveform, tx_refclk_stable is not yet asserted. Also Could You please monitor the gttxreset and txresetdone signals also. Please refer the GTP Initialization Sequence addressed in the 9th page of XAPP1097. Also make sure that, all the reset mechanism addressed properly in the tesetbench code.
I hope it helps to You.
With Regards,
Ashok
12-18-2019 01:16 AM
Hello @anilsutej ,
Most Probably this issue is because of GTP Initialization process. I noticed that in Your waveform, tx_refclk_stable is not yet asserted. Also Could You please monitor the gttxreset and txresetdone signals also. Please refer the GTP Initialization Sequence addressed in the 9th page of XAPP1097. Also make sure that, all the reset mechanism addressed properly in the tesetbench code.
I hope it helps to You.
With Regards,
Ashok
12-18-2019 01:33 AM
12-19-2019 03:26 AM
Dear Ashok,
We have the Image and Hardware path is also plroved. Thanks for the inputs.
--Anil