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Participant
Participant
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Registered: ‎01-07-2012

xapp1097 Issue with Reset and Clock : Artix-7

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Hi,

 

We are trying to Implement HD-SDI interface in Artix-7 FPGA.

We have gone through the XAPP1097 Application note and trying to simulate the files provided.

But we are stuck as the tx_usrclk stopped as reset is asserted within 5us of run time.

 

image.png

Can anyone suggest what could be the issue ?

 

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Moderator
Moderator
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Registered: ‎04-09-2019

Hello @anilsutej ,

Most Probably this issue is because of GTP Initialization process. I noticed that in Your waveform, tx_refclk_stable is not yet asserted. Also Could You please monitor the gttxreset and txresetdone signals also. Please refer the GTP Initialization Sequence addressed in the 9th page of XAPP1097. Also make sure that, all the reset mechanism addressed properly in the tesetbench code.

I hope it helps to You.

 

With Regards,

Ashok

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Moderator
Moderator
313 Views
Registered: ‎04-09-2019

Hello @anilsutej ,

Most Probably this issue is because of GTP Initialization process. I noticed that in Your waveform, tx_refclk_stable is not yet asserted. Also Could You please monitor the gttxreset and txresetdone signals also. Please refer the GTP Initialization Sequence addressed in the 9th page of XAPP1097. Also make sure that, all the reset mechanism addressed properly in the tesetbench code.

I hope it helps to You.

 

With Regards,

Ashok

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Participant
Participant
301 Views
Registered: ‎01-07-2012
Dear Ashok,

Thanks for the reply. You are right i have to wait for 1.25secs for the stable signal to assert.
I have changed that condition to sub ms and now the things are moving. There are still some problems but i will try to debug and post it here in case its not resolved
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Participant
Participant
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Registered: ‎01-07-2012

Dear Ashok,

 

We have the Image and Hardware path is also plroved. Thanks for the inputs.

 

--Anil 

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