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Visitor
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Registered: ‎07-26-2018

xapp1205 porting to picozed

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Hello,

 

I am trying to port the xapp1205 to a picozed design with carrier board. I'm struggling to get it working and need some design assistance. Can anyone point me to a resource who could potentially help? Thanks.

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Visitor
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Registered: ‎07-26-2018

Yes. It is working now. That wasn't fun. I had to iterate again and again until it worked basically changing settings in the IP blocks related to synchronization and master/slave settings.

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Moderator
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Registered: ‎11-09-2015

Hi @jyingling,

 

What will be your output on the carrier board?  Is there any ADV7511 on the carrier board?

 

The good start is to be able to get a video output. Then the full processing pipe will be easy to port


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
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Registered: ‎07-26-2018

Hello Florent,

 

Yes, my carrier board has an adv7511 and it is outputting simple video in 1080P 60Hz (solid screen color). I did this by writing a simple sync generator block and communicating i2c with the adv7511 to put it in the correct mode.

 

Now I'm trying to take that solid screen generation, write it to memory, read it from memory and then output it again to the adv7511 similarly to the xapp1205. I have the vivado block diagram setup I think correctly however, it may not be configured correctly or the SDK portion of the design may not be ported correctly. I'm struggling with the complexity.

 

I am able to pay hourly to an expert who can help if it is a reasonable rate. I have a small, well defined project that I could pass on. I am also willing to try this further myself if you have can provide guidance.

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Registered: ‎11-09-2015

HI @jyingling,

 

This is a good start if you have something displayed on the monitor.

 

For the xapp1205 you might want to use the same version as the released version. You should remove the i2c part as you already have a working one.

Make sure your clock has the same frequency as the one in the xapp. I believe the xapp uses a programmable clock. You might want to make sure you have one on your board

 

The you can add an ILA to see why you do not get video at the output. I would also monitor the locked and underflow signal from the AXI4-Stream to video out.

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

HI @jyingling,

 

Do you have any updates on this?

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
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Registered: ‎07-26-2018

Hello Florent,

 

I have done the things you mention but still I am not able to get the VDMA frame buffer working on the picozed. I had to update to 2016.4. I'm currently debugging it. Part of my question was not addressed: are there any engineering resources that I could utilize to help me with this design? Can I hire someone at an hourly rate from Xilinx or other to assist. 

 

It would be very helpful if I had a working design for the picozed that I could make modifications to. But trying to take the 2013.4 design port it to a later 2016.4 and then also port it to the picozed chip is proving very difficult for me. 

 

The current state of affairs is that I have the block diagram setup as in the xapp1205 and ported to 2016.4 and to the picozed part. I have the xdc defined properly as I got hdmi output to work by bypassing the VDMA portion of the design. When I hook up the VDMA portion I do not see any output to hdmi. As I mentioned I'm trying to debug this now using the ILA. I'll post again when I make further progress.

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Registered: ‎11-09-2015

HI @jyingling,

 

are there any engineering resources that I could utilize to help me with this design? Can I hire someone at an hourly rate from Xilinx or other to assist.

> Not from Xilinx. You can try one of our Authorized Provider. I know AVNET as a design services team but I am not sure if it is for this purpose.

You can also try to find a consultant which can help you.

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

HI @jyingling,

 

Do you have any updates on this? Were you successful in having it working?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
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Registered: ‎07-26-2018

Yes. It is working now. That wasn't fun. I had to iterate again and again until it worked basically changing settings in the IP blocks related to synchronization and master/slave settings.

View solution in original post

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