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Observer
Observer
1,639 Views
Registered: ‎08-09-2018

xapp1308 PICXO NCO output

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Hi,

I instantiated PICXO in NO_GT mode. 

I adapted the setting from xapp1308 for generating 27 MHz clock from an 15.625 KHz hsync pulse.

I found the nco output(ACC_DATA[0]) to be a pulse rather than a clock, meaning the duty cycle is not 50%. 

Furthermore the frequency of the nco output is not 27MHz as expected but 14MHz.

With this setup I generated a bitstream and forwarded the nco output to a board pin. I found the jitter to be very high - the edges were moving! 

To sum up:

-> I dont have a 50% duty cycle clock

-> frequency of the clock is not 27MHz

-> a lot of jitter on this clock

Any help is appreciated!

 

P.S.: In the attachement REF_CLK_I is connected to my hsync pulse generator(currently 15.625 KHz).

 

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xapp1308 picxo nco.JPG
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Xilinx Employee
Xilinx Employee
1,368 Views
Registered: ‎04-15-2008
@timi:
I recommend starting with the Example Design to get the NCO instantiation and connection as your starting point.

If your 15.625kHz HSync pulse is coming from a commercial device like the LMH1981 (Multi-Format Video Sync Separator, http://www.ti.com/lit/ds/symlink/lmh1981.pdf), keep in mind the stable edge is the "falling edge", so you'll need to invert (i.e. put an inverter in your FPGA) before connecting this signal to the REF_CLK_I of your PICXO NCO.

It is very important to push a reset (RESET_I port of the PICXO) on the PICXO NCO every time you change the video format of your REF_CLK_I port. You must see your ERROR_O oscillating around zero to confirm your NCO is locked.

I assume you are using the settings (R, V - hex, G1, G2, CE_DSP_RATE) for 576i (PAL) in Table 2 page 8, and values on page 9. For instance, HSync@15734Hz, NCO@27MHz, R=0, V=0x0D66, G1=01, G2=07, ACC_STEP=1, CE_DSP_RATE=0x01FF [5.5/1.000 --> C=0x59, N=5, P=4]. You may require to adjust the Fractional Pre-scale settings, refer to Table 3 and associated text.

You are correct, the NCO output won't provide a nice 27MHz clock: you'll get a "27MHz period signal" out of it, and it will look very jittery, but the goal/use-case of this NCO ref design is to push the "HSync reference" to a higher 27MHz frequency domain. The second PICXO stage (PICXO GT) will filter out this jitter and lock the TXOUTCLK to your reference.

I used 300MHz as free-running clock (so you'll get 3.33ns resolution) but 200MHz (5ns resolution) should work too.

Hope this help.
Benoit

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Moderator
Moderator
1,472 Views
Registered: ‎11-09-2015

Hi @timi,

 

Sorry about the delay on this. Are you still having issues on this?

 

If yes could you let me know:

  1. How is (are) the PICXO connected?
  2. What modifications were made to the original example design?

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
1,466 Views
Registered: ‎08-09-2018

Hi @florentw

The issue is still not solved. 

The IP is connected according to figure 3 in xapp1308 but without the PICXO_GT.

I do not use the example design. 

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Moderator
Moderator
1,462 Views
Registered: ‎11-09-2015

Hi @timi,

 

What is the clock frequency you are using to drive the PICXO core?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
1,460 Views
Registered: ‎08-09-2018
Ok sorry.
It's 200MHz on the TXOUTCLK_I input
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Xilinx Employee
Xilinx Employee
1,369 Views
Registered: ‎04-15-2008
@timi:
I recommend starting with the Example Design to get the NCO instantiation and connection as your starting point.

If your 15.625kHz HSync pulse is coming from a commercial device like the LMH1981 (Multi-Format Video Sync Separator, http://www.ti.com/lit/ds/symlink/lmh1981.pdf), keep in mind the stable edge is the "falling edge", so you'll need to invert (i.e. put an inverter in your FPGA) before connecting this signal to the REF_CLK_I of your PICXO NCO.

It is very important to push a reset (RESET_I port of the PICXO) on the PICXO NCO every time you change the video format of your REF_CLK_I port. You must see your ERROR_O oscillating around zero to confirm your NCO is locked.

I assume you are using the settings (R, V - hex, G1, G2, CE_DSP_RATE) for 576i (PAL) in Table 2 page 8, and values on page 9. For instance, HSync@15734Hz, NCO@27MHz, R=0, V=0x0D66, G1=01, G2=07, ACC_STEP=1, CE_DSP_RATE=0x01FF [5.5/1.000 --> C=0x59, N=5, P=4]. You may require to adjust the Fractional Pre-scale settings, refer to Table 3 and associated text.

You are correct, the NCO output won't provide a nice 27MHz clock: you'll get a "27MHz period signal" out of it, and it will look very jittery, but the goal/use-case of this NCO ref design is to push the "HSync reference" to a higher 27MHz frequency domain. The second PICXO stage (PICXO GT) will filter out this jitter and lock the TXOUTCLK to your reference.

I used 300MHz as free-running clock (so you'll get 3.33ns resolution) but 200MHz (5ns resolution) should work too.

Hope this help.
Benoit

View solution in original post

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Observer
Observer
1,100 Views
Registered: ‎08-14-2016

I am using your reference XAPP1315 sample codes, my application requires a 1:6  deserialization. How should I change your sample code from 1:7 to 1:6? 

Thanks,

Jim

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