02-25-2020 06:48 PM
02-25-2020 07:42 PM
Translated your question using Google Translate:
Using xilinx UltraScale + RFSOC series FPGA, it only has GTY and PS-GTR transceivers.
Can they implement 2.5G MIPI DPHY controller? How to achieve it, is there a similar application note?
XAPP1339 is created to target a particular customer system.
All the necessary files are provided with the XAPP and you need to match exact requirement of this XAPP1339 to utilize it for your design.
You may try this on your system, but there will be no technical support for this XAPP.
See also : https://forums.xilinx.com/t5/Video/MIPI-DPHY/td-p/958033
Xilinx has MIPI IP solution for UltraScale+ devices that support 2.5Gbps line rate.
Please use Vivado 2019.1.1 or Vivado 2019.2 to use this IP.
Please note that if you want to use 2019.2, we have found some known issues. please use the following patch since
Hope this helps
02-26-2020 03:39 AM
Please check US+ MPSoC datasheet. MIPI 2500Mbps is supported from Vivado 2019.1.1 using HP bank IO.
# Please note that this is Xilinx Forum, the question should be written in English. If you prefer to write in Chinese the following board is the correct place.
I believe most forum users do not understand your question.
02-27-2020 10:54 PM
>We use Ultrascale+RFSOC FPGA，I want to know whether its HP bank also support 2.5Gbps mipi interface with vivadio 2019.1.1
Yes this device supports MIPI 2.5Gbps. You can confirm using MIPI IP GUI.
But I can see that datasheet is not updated. I believe datasheet should be updated, let me cross-check with internal team
02-28-2020 09:56 PM
Thank you for answering the question.But I have another question about circuit hardware design with this solution,can you provide me some reference design document or demo schematic and so on?
03-01-2020 06:38 PM
05-03-2020 10:14 PM
Do you have any update on this ?
If you feel your questions already answered,
Please kindly marked this thread as Solved, so others can learn from your experience ?
Thanks & regards