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Visitor
Visitor
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Registered: ‎02-16-2020

xapp1339:implementing 2.5G MIPI DPHY controller by GTH transceivers,can it realize by GTY or PS-GTR?

使用xilinx UltraScale+RFSOC series FPGA,它只有GTY and PS-GTR transceivers,请问他们可以实现2.5G MIPI DPHY controller吗?如何实现,是否有类似应用说明?
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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @wxm20085007 

Translated your question using Google Translate:

[Q]
Using xilinx UltraScale + RFSOC series FPGA, it only has GTY and PS-GTR transceivers.
Can they implement 2.5G MIPI DPHY controller? How to achieve it, is there a similar application note?

[A]
XAPP1339 is created to target a particular customer system.
All the necessary files are provided with the XAPP and you need to match exact requirement of this XAPP1339 to utilize it for your design.
You may try this on your system, but there will be no technical support for this XAPP.
See also : https://forums.xilinx.com/t5/Video/MIPI-DPHY/td-p/958033

Xilinx has MIPI IP solution for UltraScale+ devices that support 2.5Gbps line rate.
Please use Vivado 2019.1.1 or Vivado 2019.2 to use this IP.
Please note that if you want to use 2019.2, we have found some known issues. please use the following patch since
https://www.xilinx.com/support/answers/73100.html

Hope this helps

Regards
Leo

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Visitor
Visitor
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Registered: ‎02-16-2020

HSSIO可以选用HP-bank的IO吗?我看HP-bank IO最高速率是1.6Gbps
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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @wxm20085007 

Please check US+ MPSoC datasheet. MIPI 2500Mbps is supported from Vivado 2019.1.1 using HP bank IO.
MIPI.png

Regards
Leo

# Please note that this is Xilinx Forum, the question should be written in English. If you prefer to write in Chinese the following board is the correct place.
   https://forums.xilinx.com/t5/%E8%B5%9B%E7%81%B5%E6%80%9D%E4%B8%AD%E6%96%87%E7%A4%BE%E5%8C%BA%E8%AE%BA%E5%9D%9B/ct-p/Chinese
   I believe most forum users do not understand your question. 

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Visitor
Visitor
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Registered: ‎02-16-2020

Dear,karnanl
We use Ultrascale+RFSOC FPGA,I want to know whether its HP bank also support 2.5Gbps mipi interface with vivadio 2019.1.1?
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Xilinx Employee
Xilinx Employee
559 Views
Registered: ‎03-30-2016

Hello @wxm20085007 

>We use Ultrascale+RFSOC FPGA,I want to know whether its HP bank also support 2.5Gbps mipi interface with vivadio 2019.1.1

Yes this device supports MIPI 2.5Gbps. You can confirm using MIPI IP GUI.


But I can see that datasheet is not updated. I believe datasheet should be updated, let me cross-check with internal team 

Regards
Leo

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Visitor
Visitor
527 Views
Registered: ‎02-16-2020

Dear,karnanl

           Thank you for answering the question.But I have another question about circuit hardware design with this solution,can you provide me some reference design document or demo schematic and so on?

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Xilinx Employee
Xilinx Employee
486 Views
Registered: ‎03-30-2016

Hello @wxm20085007 

Would you able to check PG232 Chapter 5 ?
This example design generate an application targeting ZCU102 board. It is good for a start point.
The lane rate is on 1440Mbps, but you can modify later to fit your system usecase.

Regards
Leo

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Xilinx Employee
Xilinx Employee
261 Views
Registered: ‎03-30-2016

Hello @wxm20085007 

Do you have any update on this ?
If you feel your questions already answered,
Please kindly marked this thread as Solved, so others can learn from your experience ?

Thanks & regards
Leo

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