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Explorer
Explorer
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Registered: ‎04-19-2016

xapp585 cameralink protocol first line pixel shift problem

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Hello,

 

I took the app note Xapp585 to build a Cameralink receiver and transmitter IP.  I implemented the Cameralink receiver IP, it seems that work properly. However I have realized that, there is a problem in the first line. Up to 16th pixel (16 included) is received correctly.  But after the this 16th pixel, 17th pixel is zero and then values comes. However, 17th pixel should have not to be zero. there is only 'one' pixel shift to the right, in only first line after the 16th pixel. I have used a FIFO, and I take fifo out to a Axi-Stream.

 

So what is the possible reason for this deterministic(it is seen all time ) error? 

 

Correct one : 

5180.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	64.0	68.0	72.0	76.0	80.0	84.0	88.0	92.0	96.0	100.0 ...

 

Observed one : 

5180.0  0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0	0.0     64.0	68.0	72.0	76.0	80.0	84.0	88.0	92.0	96.0	100.0 ...

 

Waiting for reply,

Best Regards,

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Moderator
Moderator
2,876 Views
Registered: ‎11-09-2015

Hi @doner_t,

 

I do not see any difference between the observed and expected results...


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Moderator
Moderator
2,877 Views
Registered: ‎11-09-2015

Hi @doner_t,

 

I do not see any difference between the observed and expected results...


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Explorer
Explorer
1,947 Views
Registered: ‎04-19-2016

Hello @florentw,

 

Normally(in correct case), 17th pixel value is 64.0, however, in our case, we received the 17th pixel is 0, 18th pixel is 64. So one pixel shift is observed after the 17th. pixel. 

 

But I have solved the this problem. This is caused by the Axi-Stream module generated in custom-IP design. Axi-Stream module added one clock delay into the data and TLAST. But Tuser is not delayed. I added one clock delay into the TUSER. So pixel shift problem is solved. 

 

Thank you again,

 

 

 

 

 

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Moderator
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Registered: ‎11-09-2015

Hi @doner_t,

 

Could you mark the issue as solved to close the thread?

 

Thanks,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Explorer
Explorer
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Registered: ‎04-19-2016
Hello,

This is solved. It is due to the unnecessary one clock cycle delay on the my pixel data.

Thank you!
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Moderator
Moderator
1,647 Views
Registered: ‎11-09-2015

Hi @doner_t,

 

Could you kindly mark a response as solution to close the forum thread?

 

Thanks,

 

Best Regards,

 

Florent

 

Happy New Year


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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