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Adventurer
Adventurer
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Registered: ‎04-05-2018

xilinx-vcu: Could not get core_enc clock

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I imitate the xilinx-zcu106-v2018.2-final.bsp to create block design. Then I use petalinux to generate image.ub and BOOT.BIN. But when I boot with SD card, the uart print this information:


[ 7.637465] xilinx-vcu xilinx-vcu: Could not get core_enc clock
[ 7.643455] xilinx-vcu: probe of xilinx-vcu failed with error -2

 

When I use this command to encode yuv to h265:

gst-launch-1.0 filesrc location=/run/media/mmcblk0p1/Runners_nv12.yuv ! videoparse width=3840 height=2160 format=nv12 framerate=60/1 ! queue ! omxh265enc gop-mode=0 gop-length=30 control-rate=2 target-bitrate=131072 quant-i-frames=20 qp-mode=0 cpb-size=500 initial-delay=500 ! filesink location="/run/media/mmcblk0p1/ouput_16.h265"

The uart print: 

Couldnt allocate dma allocator (tried using /dev/allegroIP)
ERROR: Pipeline doesn't want to pause.
ERROR: from element /GstPipeline:pipeline0/GstOMXH265Enc-omxh265enc:omxh265enc-omxh265enc0: Could not initialize supporting library.
Additional debug info:
../../../../git/gst-libs/gst/video/gstvideoencoder.c(1629): gst_video_encoder_change_state (): /GstPipeline:pipeline0/GstOMXH265Enc-omxh265enc:omxh265enc-omxh265enc0:
Failed to open encoder

 

I don't down where the problem is. Can someone give me some advice? Let me know where to work.

 Thanks!

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Moderator
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Registered: ‎11-09-2015

Re: xilinx-vcu: Could not get core_enc clock

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HI @hgtcs,

 

If you are using the ZCU106, I would recommend you to start with the BSP. Make sure the default is working. Then modify the design in the petalinux project and reload the hdf in the petalinux project created from the BSP


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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Registered: ‎11-09-2015

Re: xilinx-vcu: Could not get core_enc clock

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HI @hgtcs,

 

I imitate the xilinx-zcu106-v2018.2-final.bsp to create block design

Could you clarify what you are doing? Are you still using the ZCU106? If yes did you try directly with the pre-built images?

 

I not, what changes did you do in the design? Are you still using the BSP for the petalinux project?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎04-05-2018

Re: xilinx-vcu: Could not get core_enc clock

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No, I don't use the BSP. I create a vivado project and export the .hdf file by myself. And then I use petalinux to generate image.ub. 

 

When I generate image.ub, I use "petalinux-config" to config the system. In the configuration interface, I select "Linux Components Selection", and change them  "u-boot","arm-trusted-firmware" and "linux-kernel"  to "ext-local-src". Then I select "External linux-kernel local source settings", Enter the path: ${TOPDIR}/../components/ext_sources/<MY-KERNEL>.  The "u-boot","arm-trusted-firmware" and "linux-kernel" are from github and I download them from "https://github.com/Xilinx". 

 

After this, I select "u-boot configuration", and change "u-boot config target" to "xilinx_zynqmp_zcu106_revA_defconfig". Then I "save" and "exit". 

 

The finally I use the command "petalinux-build" to generate image.ub. 

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Registered: ‎11-09-2015

Re: xilinx-vcu: Could not get core_enc clock

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HI @hgtcs,

 

If you are using the ZCU106, I would recommend you to start with the BSP. Make sure the default is working. Then modify the design in the petalinux project and reload the hdf in the petalinux project created from the BSP


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Contributor
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Registered: ‎02-22-2008

Re: xilinx-vcu: Could not get core_enc clock

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I have the same problem. My FPGA design was working, but then I added another element in the image pipeline. Now I get the following error messages:

[    5.798635] xilinx-vcu-core a0040000.vcu: No reset gpio info from dts for vcu. This may lead to incorrect functionality if VCU isolation is removed post initialization.
[    5.960194] [drm] Cannot find any crtc or sizes
[    6.107393] xilinx-vcu xilinx-vcu: Could not get core_enc clock
[    6.116618] xilinx-vcu xilinx-vcu: failed to set logicoreIP refclk rate -22

I added a reset line in, but that caused my system to no longer boot. So I hard-coded the reset to the VCU to a 1 per the VCU datasheet/documentation (page 104). My unit boots, but I get the warning message about the core_enc clock. I've resorted to coping and pasting sections of the DTSI file from the ZCU-106 designs and crafting my own DTS file. Below is my pl.dtsi file. Any ideas on how to get the VCU working?

 

/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version:
 * Today is: Tue Mar  5 15:40:10 2019
 */


/ {
	amba_pl: amba_pl@0 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges ;
		generate_histogram_0: generate_histogram@a0120000 {
			clock-names = "ap_clk";
			clocks = <&misc_clk_0>;
			compatible = "xlnx,generate-histogram-2.5";
			interrupt-names = "interrupt";
			interrupt-parent = <&gic>;
			interrupts = <0 95 4>;
			reg = <0x0 0xa0120000 0x0 0x10000>;
			xlnx,s-axi-axilites-addr-width = <0xc>;
			xlnx,s-axi-axilites-data-width = <0x20>;
		};
		misc_clk_0: misc_clk_0 {
			#clock-cells = <0>;
			clock-frequency = <240000000>;
			compatible = "fixed-clock";
		};
		mipi_csi2_rx_subsyst_0: mipi_csi2_rx_subsystem@a0100000 {
			clock-names = "lite_aclk", "dphy_clk_200M", "video_aclk";
			clocks = <&misc_clk_1>, <&misc_clk_2>, <&misc_clk_0>;
			compatible = "xlnx,mipi-csi2-rx-subsystem-4.0", "xlnx,mipi-csi2-rx-subsystem-3.0";
			interrupt-names = "csirxss_csi_irq";
			interrupt-parent = <&gic>;
			interrupts = <0 90 4>;
			reg = <0x0 0xa0100000 0x0 0x10000>;
			xlnx,axis-tdata-width = <32>;
			xlnx,cal-mode = "NONE";
			xlnx,clk-io-swap = "false";
			xlnx,clk-lane-io-position = <0x1a>;
			xlnx,clk-lp-io-swap = "false";
			xlnx,csi-en-activelanes = "true";
			xlnx,csi-en-crc = "true";
			xlnx,csi-filter-userdatatype = "true";
			xlnx,csi-opt1-regs = "false";
			xlnx,csi-pxl-format = "RAW10";
			xlnx,csi2rx-dbg = <0x0>;
			xlnx,data-lane0-io-position = <0x2d>;
			xlnx,data-lane1-io-position = <0x20>;
			xlnx,data-lane2-io-position = <0x11>;
			xlnx,data-lane3-io-position = <0x29>;
			xlnx,dl0-io-swap = "false";
			xlnx,dl0-lp-io-swap = "false";
			xlnx,dl1-io-swap = "false";
			xlnx,dl1-lp-io-swap = "false";
			xlnx,dl2-io-swap = "false";
			xlnx,dl2-lp-io-swap = "false";
			xlnx,dl3-io-swap = "false";
			xlnx,dl3-lp-io-swap = "false";
			xlnx,dphy-lanes = <0x4>;
			xlnx,dphy-mode = "SLAVE";
			xlnx,en-active-lanes ;
			xlnx,en-bg0-pin0 = "false";
			xlnx,en-bg0-pin6 = "false";
			xlnx,en-bg1-pin0 = "true";
			xlnx,en-bg1-pin6 = "false";
			xlnx,en-bg2-pin0 = "false";
			xlnx,en-bg2-pin6 = "false";
			xlnx,en-bg3-pin0 = "true";
			xlnx,en-bg3-pin6 = "false";
			xlnx,en-clk300m = "false";
			xlnx,en-csi-v2-0 = "false";
			xlnx,en-exdesigns = "false";
			xlnx,en-timeout-regs = "false";
			xlnx,en-vcx = "false";
			xlnx,esc-timeout = <0x6400>;
			xlnx,exdes-board = "ZCU102";
			xlnx,exdes-config = "MIPI_Video_Pipe_Camera_to_Display";
			xlnx,exdes-fmc = "LI-IMX274MIPI-FMC V1.0 Single Sensor";
			xlnx,fifo-rd-en-control = "true";
			xlnx,hs-line-rate = <0x5a0>;
			xlnx,hs-settle-ns = <0x8d>;
			xlnx,hs-timeout = <0x10005>;
			xlnx,idly-group-name = "mipi_csi2rx_idly_group";
			xlnx,idly-tap = <0x1>;
			xlnx,init = <0x186a0>;
			xlnx,is-7series = "false";
			xlnx,max-lanes = <4>;
			xlnx,mipi-slv-int = <0x0>;
			xlnx,ppc = <2>;
			xlnx,share-idlyctrl = "false";
			xlnx,vc = <4>;
			xlnx,vfb ;
			csiss_ports: ports {
				#address-cells = <1>;
				#size-cells = <0>;
				csiss_port0: port@0 {
					/* Fill cfa-pattern=rggb for raw data types, other fields video-format and video-width user needs to fill */
					reg = <0>;
					xlnx,cfa-pattern = "rggb";
					xlnx,video-format = <12>;
					xlnx,video-width = <8>;
					csiss_out: endpoint {
						remote-endpoint = <&demosaic_in>;
					};
				};
				csiss_port1: port@1 {
					/* Fill cfa-pattern=rggb for raw data types, other fields video-format,video-width user needs to fill */
					reg = <1>;
					xlnx,cfa-pattern = "rggb";
					xlnx,video-format = <12>;
					xlnx,video-width = <8>;
					csiss_in: endpoint {
						data-lanes = <1 2 3 4>;
						remote-endpoint = <&sensor_out>;
					};
				};
			};
		};
		misc_clk_1: misc_clk_1 {
			#clock-cells = <0>;
			clock-frequency = <100000000>;
			compatible = "fixed-clock";
		};
		misc_clk_2: misc_clk_2 {
			#clock-cells = <0>;
			clock-frequency = <200000000>;
			compatible = "fixed-clock";
		};
		psu_ctrl_ipi: PERIPHERAL@ff380000 {
			compatible = "xlnx,PERIPHERAL-1.0";
			reg = <0x0 0xff380000 0x0 0x80000>;
		};
		psu_message_buffers: PERIPHERAL@ff990000 {
			compatible = "xlnx,PERIPHERAL-1.0";
			reg = <0x0 0xff990000 0x0 0x10000>;
		};
		sensor_iic: i2c@a0130000 {
			#address-cells = <1>;
			#size-cells = <0>;
			clock-names = "s_axi_aclk";
			clocks = <&misc_clk_1>;
			compatible = "xlnx,axi-iic-2.0", "xlnx,xps-iic-2.00.a";
			interrupt-names = "iic2intc_irpt";
			interrupt-parent = <&gic>;
			interrupts = <0 94 4>;
			reg = <0x0 0xa0130000 0x0 0x1000>;

			imx274: sensor@1a{
				compatible = "sony,imx274";
				reg = <0x1a>;
				#address-cells = <1>;
				#size-cells = <0>;
				reset-gpios = <&gpio 90 0>;

				port@0 {
					reg = <0>;

					sensor_out: endpoint {
						remote-endpoint = <&csiss_in>;
					};
				};
			};
		};

		v_demosaic_0: v_demosaic@a0140000 {
			clock-names = "ap_clk";
			clocks = <&misc_clk_0>;
			compatible = "xlnx,v-demosaic-1.0", "xlnx,v-demosaic";
			interrupt-names = "interrupt";
			interrupt-parent = <&gic>;
			interrupts = <0 91 4>;
			reg = <0x0 0xa0140000 0x0 0x10000>;
			reset-gpios = <&gpio 85 1>;
			xlnx,max-height = <2160>;
			xlnx,max-width = <3840>;
			xlnx,s-axi-ctrl-addr-width = <6>;
			xlnx,s-axi-ctrl-data-width = <32>;
			demosaic_ports: ports {
				#address-cells = <1>;
				#size-cells = <0>;
				demosaic_port0: port@0 {
					/* For cfa-pattern=rggb user needs to fill as per BAYER format */
					reg = <0>;
					xlnx,cfa-pattern = "rggb";
					xlnx,video-width = <8>;
					demosaic_in: endpoint {
						remote-endpoint = <&csiss_out>;
					};
				};
				demosaic_port1: port@1 {
					/* For cfa-pattern=rggb user needs to fill as per BAYER format */
					reg = <1>;
					xlnx,cfa-pattern = "rggb";
					xlnx,video-width = <8>;
					demosaic_out: endpoint@0 {
						remote-endpoint = <&gamma_in>;
					};
					demosaic_out2: endpoint@1 {
						remote-endpoint = <&histgram>;
					};
				};
			};
		};
		v_frmbuf_wr_0: v_frmbuf_wr@a0150000 {
			#dma-cells = <1>;
			clock-names = "ap_clk";
			clocks = <&misc_clk_0>;
			compatible = "xlnx,v-frmbuf-wr-2.1", "xlnx,axi-frmbuf-wr-v2.1";
			interrupt-names = "interrupt";
			interrupt-parent = <&gic>;
			interrupts = <0 93 4>;
			reg = <0x0 0xa0150000 0x0 0x10000>;
			reset-gpios = <&gpio 80 1>;
			xlnx,dma-addr-width = <32>;
			xlnx,dma-align = <16>;
			xlnx,max-height = <2160>;
			xlnx,max-width = <3840>;
			xlnx,pixels-per-clock = <2>;
			xlnx,s-axi-ctrl-addr-width = <0x7>;
			xlnx,s-axi-ctrl-data-width = <0x20>;
			xlnx,vid-formats = "rgb888", "bgr888", "xbgr8888", "xrgb8888", "uyvy", "y8", "vuy888", "xvuy8888", "yuyv", "nv12", "nv16";
			xlnx,video-width = <8>;
		};
		v_frmbuf_wr_1: v_frmbuf_wr@a0170000 {
			#dma-cells = <1>;
			clock-names = "ap_clk";
			clocks = <&misc_clk_0>;
			compatible = "xlnx,v-frmbuf-wr-2.1", "xlnx,axi-frmbuf-wr-v2.1";
			interrupt-names = "interrupt";
			interrupt-parent = <&gic>;
			interrupts = <0 96 4>;
			reg = <0x0 0xa0170000 0x0 0x10000>;
			reset-gpios = <&gpio 81 1>;
			xlnx,dma-addr-width = <32>;
			xlnx,dma-align = <16>;
			xlnx,max-height = <2160>;
			xlnx,max-width = <3840>;
			xlnx,pixels-per-clock = <2>;
			xlnx,s-axi-ctrl-addr-width = <0x7>;
			xlnx,s-axi-ctrl-data-width = <0x20>;
			xlnx,vid-formats = "rgb888", "bgr888", "xbgr8888", "xrgb8888";
			xlnx,video-width = <8>;
		};
		v_gamma_lut_0: v_gamma_lut@a0160000 {
			clock-names = "ap_clk";
			clocks = <&misc_clk_0>;
			compatible = "xlnx,v-gamma-lut-1.0", "xlnx,v-gamma-lut";
			interrupt-names = "interrupt";
			interrupt-parent = <&gic>;
			interrupts = <0 92 4>;
			reg = <0x0 0xa0160000 0x0 0x10000>;
			reset-gpios = <&gpio 86 1>;
			xlnx,max-height = <2160>;
			xlnx,max-width = <3840>;
			xlnx,s-axi-ctrl-addr-width = <13>;
			xlnx,s-axi-ctrl-data-width = <32>;
			gamma_ports: ports {
				#address-cells = <1>;
				#size-cells = <0>;
				gamma_port0: port@0 {
					reg = <0>;
					xlnx,video-width = <8>;
					gamma_in: endpoint {
						remote-endpoint = <&demosaic_out>;
					};
				};
				gamma_port1: port@1 {
					reg = <1>;
					xlnx,video-width = <8>;
					gamma_out: endpoint {
						remote-endpoint = <&csc_in>;
					};
				};
			};
		};
		v_proc_ss_csc: v_proc_ss@a0110000 {
			clock-names = "aclk";
			clocks = <&misc_clk_0>;
			compatible = "xlnx,v-vpss-csc";
			reg = <0x0 0xa0110000 0x0 0x10000>;
			reset-gpios = <&gpio 84 1>;
			xlnx,colorspace-support = <2>;
			xlnx,csc-enable-window = "false";
			xlnx,max-height = <2160>;
			xlnx,max-width = <3840>;
			xlnx,num-video-components = <3>;
			xlnx,samples-per-clk = <2>;
			xlnx,topology = <3>;
			xlnx,use-uram = <0>;
			xlnx,video-width = <8>;
			csc_ports: ports {
				#address-cells = <1>;
				#size-cells = <0>;
				csc_port0: port@0 {
					/* For xlnx,video-format user needs to fill as per their requirement */
					reg = <0>;
					xlnx,video-format = <12>;
					xlnx,video-width = <8>;
					csc_in: endpoint {
						remote-endpoint = <&gamma_out>;
					};
				};
				csc_port1: port@1 {
					/* For xlnx,video-format user needs to fill as per their requirement */
					reg = <1>;
					xlnx,video-format = <12>;
					xlnx,video-width = <8>;
					csc_out: endpoint {
						remote-endpoint = <&scaler_in>;
					};
				};
			};
		};
		v_proc_ss_scaler: v_proc_ss@a0180000 {
			clock-names = "aclk_axis", "aclk_ctrl";
			clocks = <&misc_clk_0>, <&misc_clk_0>;
			compatible = "xlnx,v-vpss-scaler";
			reg = <0x0 0xa0180000 0x0 0x40000>;
			reset-gpios = <&gpio 82 1>;
			xlnx,colorspace-support = <0>;
			xlnx,csc-enable-window = "true";
			xlnx,enable-csc = "true";
			xlnx,h-scaler-phases = <64>;
			xlnx,h-scaler-taps = <6>;
			xlnx,max-height = <2160>;
			xlnx,max-num-phases = <64>;
			xlnx,max-width = <3840>;
			xlnx,num-hori-taps = <6>;
			xlnx,num-vert-taps = <6>;
			xlnx,pix-per-clk = <2>;
			xlnx,samples-per-clk = <2>;
			xlnx,scaler-algorithm = <2>;
			xlnx,topology = <0>;
			xlnx,use-uram = <1>;
			xlnx,v-scaler-phases = <64>;
			xlnx,v-scaler-taps = <6>;
			xlnx,video-width = <8>;
			scaler_ports: ports {
				#address-cells = <1>;
				#size-cells = <0>;
				scaler_port0: port@0 {
					/* For xlnx,video-format user needs to fill as per their requirement */
					reg = <0>;
					xlnx,video-format = <12>;
					xlnx,video-width = <8>;
					scaler_in: endpoint {
						remote-endpoint = <&csc_out>;
					};
				};
				scaler_port1: port@1 {
					/* For xlnx,video-format user needs to fill as per their requirement */
					reg = <1>;
					xlnx,video-format = <12>;
					xlnx,video-width = <8>;
					scaler_out: endpoint {
						remote-endpoint = <&vcap_csi_in>;
					};
				};
			};
		};
		misc_clk_3: misc_clk_3 {
			#clock-cells = <0>;
			clock-frequency = <33329951>;
			compatible = "fixed-clock";
		};
		vcap_csi {
			compatible = "xlnx,video";
			dma-names = "port0", "port1";
			dmas = <&v_frmbuf_wr_0 0>, <&v_frmbuf_wr_1 0>;
			vcap_ports: ports {
				#address-cells = <1>;
				#size-cells = <0>;
				vcap_port: port@0 {
					direction = "input";
					reg = <0>;
					vcap_csi_in: endpoint {
						remote-endpoint = <&scaler_out>;
					};
				};
				vcap2_port: port@1 {
					direction = "input";
					reg = <1>;
					histgram: endpoint {
						remote-endpoint = <&demosaic_out2>;
					};
				};
			};
		};

        vcu_0: vcu@a0000000 {
            compatible = "xlnx,vcu";
            #address-cells = <2>;
            #size-cells = <2>;
            reg = <0x0 0xa0040000 0x0 0x1000>, <0x0 0xa0041000 0x0 0x1000>;
            reg-names = "vcu_slcr", "logicore";
            #clock-cells = <1>;
            clock-names = "pll_ref", "aclk", "vcu_core_enc", "vcu_core_dec", "vcu_mcu_enc", "vcu_mcu_dec";
            clocks = <&misc_clk_3>, <&misc_clk_1>, <&vcu_0 1>, <&vcu_0 2>, <&vcu_0 3>, <&vcu_0 4>;
            ranges ;
            interrupt-names = "vcu_host_interrupt";
            interrupt-parent = <&gic>;
            interrupts = <0 89 4>;
            encoder: al5e@a0000000 {
                compatible = "al,al5e";
                reg = <0x0 0xa0000000 0x0 0x10000>;
                interrupt-parent = <&gic>;
                interrupts = <0 89 4>;
            };
            decoder: al5d@a0020000 {
                compatible = "al,al5d";
                reg = <0x0 0xa0020000 0x0 0x10000>;
                interrupt-parent = <&gic>;
                interrupts = <0 89 4>;
            };
        };
	};
};
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