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Registered: ‎08-20-2019

zcu106_10g TRD and NI-DRU

Hi,

   I tried to implement the zcu106_10g TRD targetting the ZCU106. It gave the following error during optimization:

[Place 30-1174] Sub-optimal placement for an IBUFDS_GT / GT component pair. Since the IBUFDS_GT connects to the GT on a SOUTHREFCLK0/1 pin, the GT must be placed one clock region below the IBUFDS_GT. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets bd_i/gt_refclk_buf/ibufds_gt/U0/IBUF_OUT[0]] >

bd_i/gt_refclk_buf/ibufds_gt/U0/USE_IBUFDS_GTE4.GEN_IBUFDS_GTE4[0].IBUFDS_GTE4_I (IBUFDS_GTE4.O) is locked to GTHE4_COMMON_X0Y3
bd_i/vid_phy_controller/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.bd_vid_phy_controller_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.GTSOUTHREFCLK1) is locked to GTHE4_CHANNEL_X0Y0
bd_i/vid_phy_controller/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.bd_vid_phy_controller_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.GTSOUTHREFCLK1) is locked to GTHE4_CHANNEL_X0Y2
bd_i/vid_phy_controller/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.bd_vid_phy_controller_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.GTSOUTHREFCLK1) is locked to GTHE4_CHANNEL_X0Y1

...

   Looking at the XDC file sure enough the DRU clock pins are from a GT 3 Quads away to the north. This violates the DRC. In fact the TRD XDC has the following comments. They seem to anticipate this will happen: 

#SI5328 - Temporarily setting to clock within reach, can be programmed to 156.25 MHz
set_property PACKAGE_PIN U10 [get_ports {DRU_CLK_clk_p[0]}]
#Override clock placement error
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets bd_i/gt_refclk_buf/ibufds_gt/U0/IBUF_OUT[0]]

   So my question is that should I enable the CLOCK_DEDICATED_ROUTE FALSE constraint above? Will it have adverse effect on the VPhy for low resolution video quality? Or will I be better off to bring in external clock source through the SMA connected to the Quad right next to the Quad where the HDMI ports are?

 

thanks,

 

Simon

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Registered: ‎11-09-2015

Hi @simon_tam_gmail 

Are you getting error when implementing the zcu106_10g design directly with no modification?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎04-12-2017

Hello @simon_tam_gmail 

Not sure what is the reason of your experiment. If you use default optimization techniques for synthesis and implementation you should not be seeing any of these errors.

If you explain a bit about your expectations we can offer some help. At this moment we haven't done this experiment so not sure about the effect of changing the clock dedicated route to the false.

Regards

Kunal

 

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Registered: ‎11-21-2018

Hi @simon_tam_gmail 

Do you have an update on this? 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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