06-07-2019 02:46 PM
Xilinx has a Gamma Correction IP supporting up to 12-bit per component (PG004).which is now discontinued.
It is being replaced by the LogiCore Gamma LUT (PG285) which only goes up to 10-bit per component.
Does this mean that a Gamma LUT with 12-bit per component is not provided any longer?
06-12-2019 01:45 AM
Hi @jmcm ,
Yes your understanding seems correct.
If 12-bit support for gamma correction LUT is a requirement for you, I encourage you to contact your FAE about this to see if this can be implemented in future releases.
06-13-2019 05:19 AM
06-14-2019 02:37 PM
I started on the design of the LUT as I need to progress in my project. I am using 3 xpm_memory_tdpram with a read latency of 1 made out of ultra-rams to get 2 pixels per clock.
The axi-lite interface to program the LUTs is straight forward. But I'm having problems with the axi-stream master and slave interfaces.
One way maybe to do this is to duplicate the URAMs to avoid creating bubbles in the stream but I would rather stay with 3 if possible. Could you please point me to some docs or template codes to do this if there is any.
06-17-2019 12:44 AM
Hi Jacques @jmcm
Did you consider using HLS for this? What I found great with this is that you do not have to really care about the AXI4-Stream interface. You just say "read or write" data. It might save you same headhache
I made an example of video IP as part of my video series: Video Beginner Series 17: Create a Video Crop IP using HLS (part 1) and Video Beginner Series 18: Create a Video Crop IP using HLS (part 2)