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303 Views
Registered: ‎04-05-2019

2x 4Lane MIPI RX Pinning over two banks

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Hi there,

We currently try to route a 2 x 4Lane MIPI Bus (2 x (1Clk + 4Data)) to an Artix-7 200T FPGA in the SBG484 Package,
while using the two HR banks 13 and 14 for the LP and HS lines written in xapp894.

Right now I distributed each of the two 4Lanes on a separate bank, so let's say all LP/HS signals of 4Lane A to Bank 13
and all LP/HS of 4Lane B to Bank 14.

However, routing the signals to the banks shows that it would be benefical for the layouting if one differential data line of 4Lane A would be placed in bank 14
and one data line of 4Lane B in Bank 13.

I'm trying to figure out if this would work. Especially the respective clock lines sitting in other banks gives me a headache.
I don't know if the clock distribution in the Artix-7 could handle MIPI D-PHY clocks over separate banks.
I think connecting each clock to a MRCC pin would then be mandatory (instead of SRCC).

Have you any idea/experience if that would work?

Best regards,
Simon

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Moderator
Moderator
261 Views
Registered: ‎11-09-2015

Re: 2x 4Lane MIPI RX Pinning over two banks

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Hi simon.braun@sick.de ,

As per pg202 p83, the D-phy IP requires the IO to be placed in a single bank:

MIPI.JPG


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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2 Replies
Moderator
Moderator
262 Views
Registered: ‎11-09-2015

Re: 2x 4Lane MIPI RX Pinning over two banks

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Hi simon.braun@sick.de ,

As per pg202 p83, the D-phy IP requires the IO to be placed in a single bank:

MIPI.JPG


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
252 Views
Registered: ‎04-05-2019

Re: 2x 4Lane MIPI RX Pinning over two banks

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Thank you Florent,

That answers my question!
Haven't had a look on that section.

Best regards,

Simon

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