01-28-2019 11:13 AM
does anyone have an idea how to transfer an SDI video from RX to TX without VDMA (simple SDI switcher) ?
|---------------------------- Zynq ------------------------------|
3G -> RX-GTX --simple logic without vdma -> TX-GTX -> 3G
is that even possible ?
to avoid latency, i need this special case.
01-29-2019 09:08 AM - edited 01-29-2019 09:09 AM
Good morning @difi,
My reply may be off-topic, but here goes...
Can you build an AXI bus to connect the receiver and transmitter? Or, are you looking for what ammounts to simple raw-signal pass-through?
I think there are discussions about on how to go about using AXI to directly connect the RX and TX IP components.
I have a 12G pass through script, although it uses lots of resources. Easy enough to convert to 3G, though.
Do you have a decent means of measuring the latency?
01-31-2019 02:42 PM
Yes, I am looking for a very simple method for signal transfer without frame buffers.
Delays of a few flip flops would not be bad.
However, I think that it is not possible to connect the RX video stream directly to the TX video stream.
The problem, what I see are the different clocks.
It is not possible to connect the RX clock and the TX clock.
Both clocks (coming from the GTX) are outputs for the logic.
But maybe, I have a misconception ...
01-31-2019 04:34 PM
Hello Dirk (@difi),
I am sorry to say that our conversation is falling out of my areas of reasonable competence. I approach FPGA as a highly parallel software exercise, rather than as a high-speed serial processor.
To me your project looks like you are interested in performing a raw signal regeneration without any error detection, correction, or recovery.
If you hook up the RX to an AXI to the TX in your FPGA design, will the delay be acceptable?
RX will likely buffer each packet before sending it across AXI. Similarly, TX may well wait for a complete buffer and confirmation signal before transmitting. Thus, you shuld be able to compute the minimum delay based on the time delay at each point:
I believe that there are several discussions on how to build this around the Forum. It is not something that I have ever done.
Going out on a limb - I do not think that the FPGA is capable of carrying a 12GHz serial bit-stream internally. Also, the acceptable transmission jitter is likely to require that the TX logic have a minimum of two or three AXI bus packets worth of bits queued before it can begin clocking them out. Let's say it requires three 32-bit transfers, 100 bits. This corresponds to (roughly) 8 nsec of delay, at best. Can you tolerate this level of delay?
The thing is that I do not know if it is even possible to hook up the components such that they will behave this way.
There are other, smarter people than I who can probably coach you to a truly minimal pass-through time.
Good luck my friend.