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Visitor sabitha
Visitor
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Registered: ‎07-11-2019

3G-SDI Zynq Processor

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Hi,

I have designed 3g sdi using Zynq processor, want to reduce jitter from recovered clock without using external PLL ,there is any other way to reduce the jitter in software ,please  let me know

Thanks & regards

Sabitha M

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Xilinx Employee
Xilinx Employee
165 Views
Registered: ‎04-15-2008

Re: 3G-SDI Zynq Processor

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Hi @sabitha,

Sorry a bit long post.  Hope you'll find it useful.

The app note for 7 Series PICXO is xapp589.  The xapp1308 describes an additional feature using the PICXO in non-GT mode to filter low wander frequencies from an HSync (running in kHz) when it is connected to the REF_CLK_I of the PICXO (i.e. syncing to a Black Burst).

To get you going, I recommend you create the Reference Design from xapp589 (targeting a KC705 for GTX or AC701 for GTP) and review how the PICXO is implemented in a simple design; the xapp589 tells you how to generate the Reference Design.  Keep in mind, this Reference Design is not SDI specific.  However in the PICXO Lounge, you will also notice a link to "Triple-Rate SDI Pass-Through VCXO Replacement Reference Design (ZIP)" targeting Virtex-6, you could review that code too.

If you are targeting the larger Zynq-7000 devices (7z030 or larger), the GTs are the same as the Kintex-7 GTX.  All the TXPI updates from the PICXO must go through the DRP interface.  An arbitration mechanism must be used between the normal GTX operations for SDI (mostly RX CDR updates, and Rx/Tx initialization) and the PICXO TXPI updates.  The PICXO implements an arbitration mechanism, see xapp589 for the description.

Xilinx has not released an official app note or reference design for 7 Series triple rate SDI passthrough.  However, see the picture below showing where the PICXO fits in xapp592 for a passthrough application.  You'll notice the multiplexer connected to the REF_CLK_I port of the PICXO, it is choosing between the RX Recovered Clock for HD or 3G, and RX_CE signal for SD.

Kintex7_SDI_pass-through_with_PICXO.v2.1.png

You must set specific coefficient values for your PICXO, depending on the Tx mode you wish to drive.  Here are a few recommendations, you'll need to experiment to fine-tune the Gain numbers (G1, G2) in function of your system requirements.

HD mode (tx_mode = 00 or 11)
G1_F = 10 dec (fast acquisition)
G2_F = 18 dec 
G1_S =  2 dec (low output jitter)
G2_S = 14 dec 
R = 218 dec (actual count value R'=218+2=220)
V = 218 dec ((actual count value V'=218+2=220; PD freqencies 339kHz)
ACCSTEP = "0100"    (  4 decimal)
DSPRATE = 0x07FF (2047 decimal)

SD mode (tx_mode = 01)
G1_F = 10 dec (fast acquisition)
G2_F = 18 dec
G1_S = 2 dec (low output jitter)
G2_S = 14 dec
R = 98 dec (actual count value R'=218+2=220)
V = 548 dec (actual count value V'=548+2=550; PD freqencies 270kHz)
ACCSTEP = "0010"   ( 2 decimal)
DSPRATE = 0x07FF (2047 decimal)

3G mode (tx_mode = 10)
G1_F = 10 dec (fast acquisition)
G2_F = 18 dec
G1_S = 2 dec (low output jitter)
G2_S = 14 dec
R = 548 dec (actual count value R'=548+2=550)
V = 548 dec (actual count value V'=548+2=550; PD freqencies 270kHz)
ACCSTEP = "0010" ( 2 decimal)
DSPRATE = 0x07FF (2047 decimal)

 

Finally, the quality of the both XOs (148.5MHz and 148.35MHz) is important to meet the SDI jitter spec.  Here is some information about GT Ref clock.

  • The quality of the GT reference clocks’ Phase Noise must be at least equal to Answer Record #44549 - 7 Series FPGA GTX/GTH/GTP Transceivers - Reference clock phase noise masks
    • The Figure below shows the plots for a few reference clocks in comparison to AR#44549, namely the TamaDevice used on TED TB-FMCH-3GSDI2A and two Silicon Labs devices Si511 and Si531.
    • If the GT ref clocks’ Phase Noise do not comply with this requirement, the customer may observe more jitter at the GT TX output due to the ref clocks jitter.
  • Make sure there is no coupling noise due to the power supplies around their FPGA.

phase_noise_AR44549.png

 

Hope this help.  Good luck!

Benoit

6 Replies
Moderator
Moderator
214 Views
Registered: ‎11-09-2015

Re: 3G-SDI Zynq Processor

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HI @sabitha 

To do 3G-SDI you need to use the Gigabit Transceivers and for this you need a GT ref clock. Thus you need an external clock.

PS: Are you using the Xilinx SDI IP?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor sabitha
Visitor
208 Views
Registered: ‎07-11-2019

Re: 3G-SDI Zynq Processor

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Hi Florent,

yes. am using Xilinx SDI IP(zynq-7000), i haven't used jitter for recovered clock that why we go for PIXCO ,but we didnt get proper document for PIXCO IP

Regards

sabitha M

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Moderator
Moderator
203 Views
Registered: ‎11-09-2015

Re: 3G-SDI Zynq Processor

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HI @sabitha 

The documentation for PICXO is mainly xapp1308.

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor sabitha
Visitor
191 Views
Registered: ‎07-11-2019

Re: 3G-SDI Zynq Processor

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we have using xapp592 pass-through design example. xapp592 design used only one clock (148.5mhz) on receiver side. transimtter used recovered clock from receiver. the design receives the data, but it does not transmit. we found the problem on recovered clock side. how can i use picxo IP in this design. Is there any design for sdi pass-through for zynq using two reference clock ?

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Highlighted
Xilinx Employee
Xilinx Employee
166 Views
Registered: ‎04-15-2008

Re: 3G-SDI Zynq Processor

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Hi @sabitha,

Sorry a bit long post.  Hope you'll find it useful.

The app note for 7 Series PICXO is xapp589.  The xapp1308 describes an additional feature using the PICXO in non-GT mode to filter low wander frequencies from an HSync (running in kHz) when it is connected to the REF_CLK_I of the PICXO (i.e. syncing to a Black Burst).

To get you going, I recommend you create the Reference Design from xapp589 (targeting a KC705 for GTX or AC701 for GTP) and review how the PICXO is implemented in a simple design; the xapp589 tells you how to generate the Reference Design.  Keep in mind, this Reference Design is not SDI specific.  However in the PICXO Lounge, you will also notice a link to "Triple-Rate SDI Pass-Through VCXO Replacement Reference Design (ZIP)" targeting Virtex-6, you could review that code too.

If you are targeting the larger Zynq-7000 devices (7z030 or larger), the GTs are the same as the Kintex-7 GTX.  All the TXPI updates from the PICXO must go through the DRP interface.  An arbitration mechanism must be used between the normal GTX operations for SDI (mostly RX CDR updates, and Rx/Tx initialization) and the PICXO TXPI updates.  The PICXO implements an arbitration mechanism, see xapp589 for the description.

Xilinx has not released an official app note or reference design for 7 Series triple rate SDI passthrough.  However, see the picture below showing where the PICXO fits in xapp592 for a passthrough application.  You'll notice the multiplexer connected to the REF_CLK_I port of the PICXO, it is choosing between the RX Recovered Clock for HD or 3G, and RX_CE signal for SD.

Kintex7_SDI_pass-through_with_PICXO.v2.1.png

You must set specific coefficient values for your PICXO, depending on the Tx mode you wish to drive.  Here are a few recommendations, you'll need to experiment to fine-tune the Gain numbers (G1, G2) in function of your system requirements.

HD mode (tx_mode = 00 or 11)
G1_F = 10 dec (fast acquisition)
G2_F = 18 dec 
G1_S =  2 dec (low output jitter)
G2_S = 14 dec 
R = 218 dec (actual count value R'=218+2=220)
V = 218 dec ((actual count value V'=218+2=220; PD freqencies 339kHz)
ACCSTEP = "0100"    (  4 decimal)
DSPRATE = 0x07FF (2047 decimal)

SD mode (tx_mode = 01)
G1_F = 10 dec (fast acquisition)
G2_F = 18 dec
G1_S = 2 dec (low output jitter)
G2_S = 14 dec
R = 98 dec (actual count value R'=218+2=220)
V = 548 dec (actual count value V'=548+2=550; PD freqencies 270kHz)
ACCSTEP = "0010"   ( 2 decimal)
DSPRATE = 0x07FF (2047 decimal)

3G mode (tx_mode = 10)
G1_F = 10 dec (fast acquisition)
G2_F = 18 dec
G1_S = 2 dec (low output jitter)
G2_S = 14 dec
R = 548 dec (actual count value R'=548+2=550)
V = 548 dec (actual count value V'=548+2=550; PD freqencies 270kHz)
ACCSTEP = "0010" ( 2 decimal)
DSPRATE = 0x07FF (2047 decimal)

 

Finally, the quality of the both XOs (148.5MHz and 148.35MHz) is important to meet the SDI jitter spec.  Here is some information about GT Ref clock.

  • The quality of the GT reference clocks’ Phase Noise must be at least equal to Answer Record #44549 - 7 Series FPGA GTX/GTH/GTP Transceivers - Reference clock phase noise masks
    • The Figure below shows the plots for a few reference clocks in comparison to AR#44549, namely the TamaDevice used on TED TB-FMCH-3GSDI2A and two Silicon Labs devices Si511 and Si531.
    • If the GT ref clocks’ Phase Noise do not comply with this requirement, the customer may observe more jitter at the GT TX output due to the ref clocks jitter.
  • Make sure there is no coupling noise due to the power supplies around their FPGA.

phase_noise_AR44549.png

 

Hope this help.  Good luck!

Benoit

Moderator
Moderator
110 Views
Registered: ‎11-09-2015

Re: 3G-SDI Zynq Processor

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HI @sabitha 

Is everything clear for you on this? What @benoitp 's reply helpful?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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