3G SDI to AXI4 Stream

[pgrangeray]

Hello guys,

Question about 3G SDI and AXI4 stream : 

I use the KC705 SDI demo code to extract pixels data of an 3G SDI video input .

I need to convert YUV to RGB, so i expected to use the IP available in the catalog.

But, that IP needs AXI4 as input!

So, how to transform 3G SDI data (no HSYNC no VSYNC) to AXI4? IP "Video in to AXI4 Stream" needs HSYNC and VSYNC?

Maybe, there is an other solution to convert properly and efficiently to RGB?

Thank you

Paul

France

[watari]

Hi @pgrangeray

Did you implement the following SDI IP ?

https://www.xilinx.com/support/documentation/ip_documentation/v_smpte_sdi/v3_0/pg071-v-smpte-sdi.pdf

This IP's output is AXI4 stream.

Also, if you want to convert color format from RGB to YUV, I recommend to use "Color Correction Matrix".

This is for ASI4 stream.

Thank you.

Best regards,

[pgrangeray]

Yes, i do.
But i don't have the option for AXI interface...
And it is packed into other modules (KC705 SDI demo).

[watari · Accepted solution]

Hi @pgrangeray

Could you refer the following URL ?

https://www.xilinx.com/products/intellectual-property/sdi_video_bridge.html

I already implemented DisplayPort IP (xapp1271) on KC705.

This IP (DisplayPort IP) is smiler 3G SDI IP.

Because of HDMI IP, DP IP and 3G SDI are family for video interface.

Thank you.

Best regards,

[pgrangeray]

Hi @watari

Oh great! I ask Xilinx for that IP.
I wait for it and its documentation before go forward.
Thank you

[pgrangeray]

Hi @watari

IP received.

Integration, OK.

But with AXI4 Stream, i lost the line identification transmitted by SDI Core.

In an other topic ( https://forums.xilinx.com/t5/7-Series-FPGAs/DRAM-utilisation-for-video-processing/m-p/770586#M21957 ), i speak about picture incrustation.

From your opinion, is AXI4 Stream usefull for picture incrustation?

I thought proceed line by line (read line in DRAM and if necessary change pixel in Rx video line), so i need line number.

Any suggestion?

Thank you

[watari]

Hi @pgrangeray

> From your opinion, is AXI4 Stream usefull for picture incrustation?

Could you mention about more detail ?

I can not suggest to you without your detail explanation.

Because of it depends on what you want to do.

For example,

Do you need counter value for your design, like vertical counter ? (1)

Or

Do you need to synchronize input like VSYNC to output video, like GENLOCK ? (2)

Or

Other ? (3)

If your answer is (1), could you refer the following URL ?

https://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v4_0/pg044_v_axis_vid_out.pdf

Thank you.

Best regards,

[watari]

Hi @pgrangeray

Sorry. I don't refer your original post. (ddr)

Oh. I have an experience to rotate some picture via DRAM and our designed memory controller on ASIC.

In this case, I suggest to use native video format or AXI4 to do rotate the picture. (90 degree, 180 degree, 270 degree and mirror.)

For native video format, you need consider DRAM controller to improve performance.

For AXI4, it is easy way to archive what you want to do. But you should prepare high performance DRAM.

Thank you.

Best regards,

Thank you.

Best regards,

[pgrangeray]

For the frame rotation, we will use MIPI DSI Command (set_address_mode) for row/column swap. I am not sure if it works but it seems to...
Because rotation from DRAM (i.e change line 1080 times just t extract one row) is too long.

The new issue is pictogram incrustation.
I can't know in advance where to incrust pictograms.
I was thinking to save in DRAM a picture (1920*1080 pixels, same size as video input) representing the inlay. This picture in DRAM does not change, except if pictogram needs to be changed.
My idea :
I create video mix line by line :
- read one line in DRAM and store it in BRAM (the line corresponding the the next video line received)
- receive one video line and store it in BRAM (new line every 15µs).
- Iteration on BRAMs and replace video line by pictogram if necessary
- output video line

Other possibility, buy OSD IP core, but it's too expensive...

[florentw]

Hi @pgrangeray,

For the frame rotation, we will use MIPI DSI Command (set_address_mode) for row/column swap. I am not sure if it works but it seems to...
Because rotation from DRAM (i.e change line 1080 times just t extract one row) is too long.

I must say that I don't know this MIPI command.

But if you cannot doing using MIPI DSI, it has been done using AXI DMA or AXI VDMA. See for example:

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Video-rotation-using-axi-vdma/td-p/447788

Other possibility, buy OSD IP core, but it's too expensive...

-> it is also discontinued, so you won't have it in 2017.1. It has been replaced by the video mixer IP.

Regards,

Florent

[pgrangeray]

Hi @florentw

I wasn't aware of this rotation using DMA or VDMA. I take a look on it.

In find OSD in Vivado 2017, video mixer too. Both aren't free, few thousand €...