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Voyager
Voyager
1,670 Views
Registered: ‎05-30-2017

3g-sdi bandwidth 4 input 4 output MIG DDR3

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Hello I'm doing a project on artix 7 xc200 and I'm using Vivado 2017.4. The project that I'm developing has 4 3g-sdi input and 4 3g-sdi output. I would want to write in DDR3 using mig the 4 input and to read from DDR3 the 4 output. So I need of a total bandwidth of

2.970 Gbit/s * 8 = 2.970 Gbyte/s = 2970MByte/s . Is this bandwidth achievable evantually bypassing also mig interface? This is a video application so is very optimal about bandwidth and furthermore I read RAM cyclically and so I can avoid refreshing RAM. Thank you.

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Explorer
Explorer
1,990 Views
Registered: ‎07-17-2014

回复: 3g-sdi bandwidth 4 input 4 output MIG DDR3

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@pierlum

Yes, no problem. I've done a lot of similar projects in Artix 7.

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Explorer
Explorer
1,627 Views
Registered: ‎07-17-2014

回复: 3g-sdi bandwidth 4 input 4 output MIG DDR3

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@pierlum

i'm sorry, i don't understand what you want to ask.

however, the above situation generally needs to be cached by ddr, and there is no problem with bandwidth.

Voyager
Voyager
1,613 Views
Registered: ‎05-30-2017

回复: 3g-sdi bandwidth 4 input 4 output MIG DDR3

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Sorry for my bad english and tahnks for the reply. I would know if I can achieve a bandwith of  2970MByte/s with Artix 7, MIG and DDR3. Thank you

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Explorer
Explorer
1,991 Views
Registered: ‎07-17-2014

回复: 3g-sdi bandwidth 4 input 4 output MIG DDR3

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@pierlum

Yes, no problem. I've done a lot of similar projects in Artix 7.

View solution in original post

Voyager
Voyager
1,593 Views
Registered: ‎05-30-2017

回复: 3g-sdi bandwidth 4 input 4 output MIG DDR3

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Thank you very much. I'm thinking to bypass axi4 to optimize bandwidth communicating directly with MIG. Which is the maximum bandwith that you achieved? Did you clock RAM with 400 MHz? Thank you.

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Voyager
Voyager
1,572 Views
Registered: ‎05-30-2017

回复: 3g-sdi bandwidth 4 input 4 output MIG DDR3

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As you can see from the simulation below I simulated mig to extimate max bandwith using this simple verilog code to drive mig signals. Actually I only simulated writing.

 

 

 


//app_cmd[2:0] = 3'b000

always @ ( * ) {app_en,app_wdf_end,app_wdf_wren} <= {3{app_rdy&app_wdf_rdy}}; always @ (posedge ui_clk) app_addr[28:0] <= ui_clk_sync_rst ? 29'h00 : (app_en ? app_addr[28:0] + 29'd32 : app_addr[28:0]); always @ ( * ) app_wdf_data[255:0] <= {8{3'b000,app_addr[28:0]}};

I'm clocking RAM with 400 MHz and PHY is 4:1. Ram is DDR3 32 bit and so MIG data width is 256 bit. 

 

 

Real bandwidth = Peack Bandwidth * efficency

 

Peack Bandwidth = 2 * 400*10^6 * 32 = 25,6 Gbit/s = 3,2 GByte/s

 

Looking at the simulation below I estimated an efficency of 80%. In a period of 40 ui_clk delimited by the two vlue markers I have 32 valid write enable.

 

 So Real Bandwith = 3,2 GByte/s * 0,8 = 2,56Gbye/s (ignoring refresh so real value is minor than this) and I would need of a bandwidth of 2,97GByte/s.

My simulation is not good or maybe did you use a 64 bit DDR3? Thank you.

 

 

Webp.net-compress-image.jpg

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Voyager
Voyager
1,560 Views
Registered: ‎05-30-2017

回复: 3g-sdi bandwidth 4 input 4 output MIG DDR3

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I modified previous code. I did a mistake. app_addr[28:0] are double words and not bytes. Now I add +8 to address each time I write. In this way I write adiacent RAM location. So my code now is

 

 

always @ (posedge ui_clk) app_addr[28:0] <= ui_clk_sync_rst ? 29'h00 : (app_en ? app_addr[28:0] + 29'd8 : app_addr[28:0]);

I also disabled auto refresh manual editing mig_7series_v4_0_rank_cntrl.v assigning 0 value to refresh_request editing this part of code line 464

 

      // assign refresh_request = init_calib_complete &&
     // (~|refresh_bank_r ||
     // ((refresh_bank_r != nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]) && 
     //~my_rank_busy));
  
 assign refresh_request = 1'b0;

In my application I need to read ciclically RAM and so I can avoid refresh.

In this way now efficency is 94,07% and real bandwidth is 3Gbyte and I need 2,97 GByte/s.

 

 

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Moderator
Moderator
1,509 Views
Registered: ‎11-09-2015

回复: 3g-sdi bandwidth 4 input 4 output MIG DDR3

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HI @pierlum,

 

If I understand, you have now what you needed? If this is the case, could you kindly close the topic by marking a reply from @avcon_lee as accepted solution (button accept as solution while logged in).

 

If not could you clarify where you are.

 

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**