UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
903 Views
Registered: ‎03-17-2011

ADV7282A to AXI Stream

Jump to solution

Hello All,

 

I need to acquire a input PAL/NTSC signal form a Analog Device ADV7282A.

Format is YcbCr 4:2:2 following the BT.656 standard.

 

I've seen the following post : link

I believe I can get some inspiration from this reference design.

This one uses a VGA ctrl which give a pixel format in RGB 4:4:4. It is different from what I need.

 

Do I need to create an interface from my input pixels in YcbCr 4:2:2 BT.656 standard and output them in ?? along with HSYNC, VSYNC and field? Or the video_in to axi4s IP is directly capable of acquiring YcbCr 4:2:2 BT.656  pixels?

 

Thanks.

 

Sébastien

--Sebastien
0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
1,193 Views
Registered: ‎11-09-2015

Re: ADV7282A to AXI Stream

Jump to solution

Hey Sébastien @sebo,

 

Thank you for reading my Xilinx Video Beginner Series 2 ;)

 

Just note that I wouldn't call the file attached a reference design (I consider a reference design as a fully validated example while here it just shows a feature). I would call it tutorial design :)

 

Then as per @tedbooth I would say that the video in to AXI4-Stream IP can support YCbCr422.

 

However going through the BT656 and the ADV7282A datasheet there is few things you might want to investigate:

  • Will your input (or output from ADV7082A) be a digital input? From both document (read quickly) I am not sure. The design I made is a bit misleading when I say VGA as VGA is a analog interface while I am using it as digital data (so it would mean that in my test bench the VGA correspond to a VGA input after an ADC).
    From the ADV7282A it seems that it is doing the conversion between Analog to Digital so you should be getting digital signals
    ADV.JPG
  • Then from the BT656, they are talking about NRZ encoding. In my design, the VGA value are non-encoded value.
  • Then I do not see the timing signals for the ADV7282A. You might need to recreate them to use the video In to AXI4S IP (it might be easier to create the AXI4S signals by yourself if you need to recreate this).
  • So assuming the data is digital, without encoding and with the timing signals, yes you can input YCbCr 422. From what I understand from the BT656 is that the value are between 1 and 254 so you can assume that they are between 0 and 256. But the AXI4-Stream is quite transparent to which standard you are using. It will just transmit the data without carring how it is formated

 

Hope that helps,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
4 Replies
Explorer
Explorer
853 Views
Registered: ‎03-28-2016

Re: ADV7282A to AXI Stream

Jump to solution

The Video In to AXI4S IP supports YCrCb 4:2:2 input.  Here is a link to the Product Guide

 

https://www.xilinx.com/support/documentation/ip_documentation/v_vid_in_axi4s/v4_0/pg043_v_vid_in_axi4s.pdf

 

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
Explorer
Explorer
845 Views
Registered: ‎03-17-2011

Re: ADV7282A to AXI Stream

Jump to solution

Thanks Ted,

 

I was looking into that IP. However, I'm wondering is this could be working with the external decoder ADV7282A.

The chip does not provide the video timings. Only 8-bits and the clock.

The timings are included within the pixel flow like stated in the BT.656 standard (EAV/SAV).

 

So, I think  I need to develop an front-end interface to deliver proper signals to the Video In to AXI4S IP.

 

what do you think?

 

thanks.

 

Sébastien

--Sebastien
0 Kudos
Moderator
Moderator
1,194 Views
Registered: ‎11-09-2015

Re: ADV7282A to AXI Stream

Jump to solution

Hey Sébastien @sebo,

 

Thank you for reading my Xilinx Video Beginner Series 2 ;)

 

Just note that I wouldn't call the file attached a reference design (I consider a reference design as a fully validated example while here it just shows a feature). I would call it tutorial design :)

 

Then as per @tedbooth I would say that the video in to AXI4-Stream IP can support YCbCr422.

 

However going through the BT656 and the ADV7282A datasheet there is few things you might want to investigate:

  • Will your input (or output from ADV7082A) be a digital input? From both document (read quickly) I am not sure. The design I made is a bit misleading when I say VGA as VGA is a analog interface while I am using it as digital data (so it would mean that in my test bench the VGA correspond to a VGA input after an ADC).
    From the ADV7282A it seems that it is doing the conversion between Analog to Digital so you should be getting digital signals
    ADV.JPG
  • Then from the BT656, they are talking about NRZ encoding. In my design, the VGA value are non-encoded value.
  • Then I do not see the timing signals for the ADV7282A. You might need to recreate them to use the video In to AXI4S IP (it might be easier to create the AXI4S signals by yourself if you need to recreate this).
  • So assuming the data is digital, without encoding and with the timing signals, yes you can input YCbCr 422. From what I understand from the BT656 is that the value are between 1 and 254 so you can assume that they are between 0 and 256. But the AXI4-Stream is quite transparent to which standard you are using. It will just transmit the data without carring how it is formated

 

Hope that helps,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Explorer
Explorer
835 Views
Registered: ‎03-17-2011

Re: ADV7282A to AXI Stream

Jump to solution

Hi Florent,

 

Ok. I need to develop a front end to create the timings then. I'll see if I finally need the IP in the end.

 

thanks again for your help.

 

See you.

--Sebastien
0 Kudos