08-13-2019 08:32 AM
My Requrement : I have a Custom video IP and Frames need to be written in to SDRAM using AXI VDMA and also Read back the same to stream on any video interface.
I started from Example Project which was set to VSIZE = 1; I have chnaged the Register to 10 but my simulations are not moving forward. Following are the sanpshots of the waveforms
Only one Line is written and my stream module is issuing the lines but there is nothing is happening on s2mm ports.
Following are the Register Configurations
My Stream Input Frequency is 25MHz and s2mm,m2ss clocks are running @ 50 MHz
and VDMA settings are
Please suggest if there is wrong in register settings and also the waveforms are not following the timing waveforms given in the AXI VDMA document.
And also please point me to a correct documentation which explains the handshake properly especially for the signals TREADY -- TVALID , BREADY -- BVALID and TLAST
08-19-2019 03:25 AM
You might want to have a look at my Video Series and specifically the following one which are showing example using the VDMA:
They are all running in HW (not in simulation) but you can still read them as reference
For documentation around TREADY -- TVALID , BREADY -- BVALID and TLAST, you might want to get the AXI4 and AXI4-Stream spec from ARM website (it is free, you just need to register). Also, refer to UG934 for AXI4-Stream specific use for Xilinx Video IPs
Then, starting by looking at your configuration:
You also might want to read back the register value of the status registers (0x04 and 0x34) to see if any errors are flagged. You might want to refer to my video series 25 for some help solving those
This should help you doing some progresses.
08-19-2019 06:50 AM