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1,089 Views
Registered: ‎12-25-2018

AXI video streaming protocol for HDMI Transmitter Subsystem v3.1 (Vivado 2018.3)

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Hi,

I got some enquiries regarding the AXI video streaming protocol for HDMI Tx subsystem v3.1.

1) What is the mode (axi stream to video out IP) use inside the HDMI Tx subsystem? Master or slave mode? If Master mode, the streaming video data must come from frame buffer in order for the HDMI Tx SS to lock??

2) Besides following the AXI video stream protocol for the streaming interface, what other specific requirements are needed for the HDMI subsystem to lock to the incoming streaming data?

3) We intend to design a custom AXI video stream master to connect to the stream interface of HDMI Tx SS, how many video frames are needed in order for the HDMI Tx SS to lock?

Regards

YE

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Registered: ‎12-25-2018

Re: AXI video streaming protocol for HDMI Transmitter Subsystem v3.1 (Vivado 2018.3)

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Hi Florent,

Not yet. Will close this issue for now. Thanks.

 

Regards

YE

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Registered: ‎10-04-2017

Re: AXI video streaming protocol for HDMI Transmitter Subsystem v3.1 (Vivado 2018.3)

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yan-eng.ang@leica-microsystems.com,

 

A1. The streaming data needs to match the requirements in UG934. It does not need to come from a frame buffer. See our example designs. (Chapter 5 PG235)

2019-04-30 14_39_39-Xilinx Documentation Navigator 2019.1 -  http___www.xilinx.com_support_documenta.png

A2. The resolution needs to match what the HDMI core is configured for and the stream needs to run fast enough not to starve the HDMI core. Ex. Hsize and Vsize need to be correct.

 

A3. I am not sure the exact number and it may change slightly from implementation to implementation, but I know it is a few. If you want a better answer, you could put an ILA into one of the example designs and trigger on tuser and see when locked goes high.

 

-Sam

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Registered: ‎12-25-2018

Re: AXI video streaming protocol for HDMI Transmitter Subsystem v3.1 (Vivado 2018.3)

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Hi Sam,

Thanks for your reply. I have the ZCU102 board that implements HDMI Tx SS successfully using MIPI CSI2 receiver at 3840 x 2160 60Hz frame rate. (4k60hz video is seen on the monitor) The axi video streaming data comes from frame buffer using VDMA.

Now we intend to design custom logic to bring axi video stream to the stream interface of HDMI Tx SS. We do not want the video frame to come from frame buffer to reduce latency from camera source to HDMI Tx SS.

Camera input video (4K60Hz) frame => custom logic creating axi video stream (4K60Hz) => Axi video stream of HDMI Tx SS.

Since the example design for HDMI Rx SS can connect to the HDMI Tx SS directly, I assume the HDMI Tx SS is at Slave Mode. Am I right??

I have a look on the datasheet for HDMI Rx SS and it consists of v_vid_in_axi4s IP. It has additional "drop_en" signal that is connected to the "bridge_pixel_drop" signal of HDMI Rx SS. The standalone IP for v_vid_in_axis does not have this signal. The datasheet for HDMI Tx SS also have "bridge_pixel_repeat" signal connected to "repeat_en" signal of v_axi4s_vid_out IP. Standalone IP for v_axi4s_vid_out IP do not have this signal. So in short, in order to make the passthru works, those signals are needed in order for HDMI Tx SS to lock on to the AXI video stream data?

I have perform a test using v_vid_in_axi4s IP that is connected to the axi stream interface of HDMI Tx SS. But the SS never asserts the locked signal. Overflow is observed on v_vid_in_axi4s. The v_vid_in_axi4s is running in common mode using 300Mhz for aclk which is enough to transport 4k60hz at 2pixel/clk. The native video interface for v_vid_in_axi4s is driven by VTC configured for 3840x2160. Another VTC is connected to the v_vid_in_axi4s IP as detector mode. 4k resolution is detected on this VTC. (1920 hsize(2pix/clk) and 2160 vsize)

The purpose of the above test is to verify whether axi video stream of HDMI TX SS can be lock. But the SS never asserts the locked signal. It seems like for the HDMI Tx SS to lock to the incoming axi video stream data, it has certain requirements and is non-trivial.

 

Regards

YE

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Registered: ‎10-04-2017

Re: AXI video streaming protocol for HDMI Transmitter Subsystem v3.1 (Vivado 2018.3)

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Hi yan-eng.ang@leica-microsystems.com,

Since the example design for HDMI Rx SS can connect to the HDMI Tx SS directly, I assume the HDMI Tx SS is at Slave Mode. Am I right??

I am assuming you are talking about the data interface? If you are using AXI4-Stream then yes it is an AXI Slave interface. One note is that if you do not have a frame buffer in your design and your RX is not on the same clock as your TX, you may run into an overflow/underflow issue that can not be fixed without having the frame buffer repeat/drop a frame for you. 

The purpose of the above test is to verify whether axi video stream of HDMI TX SS can be lock. But the SS never asserts the locked signal. It seems like for the HDMI Tx SS to lock to the incoming axi video stream data, it has certain requirements and is non-trivial.

If you are testing to see if the video stream of the HDMI TX can lock to your custom IP, why not use the HDMI TX? It seems like you may be configuring the AXI4-Stream to video out IP incorrectly. The best way to see if the IP will work is to use the IP and not try to recreate the SubSystem yourself. 

 

-Sam

When testing with the HDMI TX subsystem, you can probe the locked signal from the core. 

 

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Registered: ‎12-25-2018

Re: AXI video streaming protocol for HDMI Transmitter Subsystem v3.1 (Vivado 2018.3)

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Hi Sam,

I am using Video In to AXI4-S IP to connect to the AXI4-S interface of HDMI Tx SS. I use VTC to generate native video timing (3840x2160 resolution) to the Video In to AXI4-S IP. Overflow is seen on this IP.

The Video In to AXI4-S IP is running in common mode. 300MHz clk is running on both Video In to AXI4-S IP and HDMI Tx SS. The HDMI Tx SS locked signal is connected to LED. But never gets asserted.

I am using ILA to verify the AXI4-Streaming signals from Video In to AXI4-S to  AXI4-S interface of HDMI Tx SS. The transactions looks ok but overflow is seen on Video In to AXI4-S IP. 

What is the right way to handle overflow problem? Can I connect Video In to AXI4-S to  AXI4-S interface of HDMI Tx SS directly?

 

Regards

YE

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Mentor watari
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Registered: ‎06-16-2013

Re: AXI video streaming protocol for HDMI Transmitter Subsystem v3.1 (Vivado 2018.3)

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Hi yan-eng.ang@leica-microsystems.com 

 

I suggest you to share your block diagram or board design to resolve and clear this issue.

Also, clock information, too.

 

I guess it seems clock frequency issue.

 

Best regards,

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Registered: ‎10-04-2017

Re: AXI video streaming protocol for HDMI Transmitter Subsystem v3.1 (Vivado 2018.3)

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Hi yan-eng.ang@leica-microsystems.com,

 

As Watari has requested, please share your block diagram to help us see your issue.

For the bridge (Video in to AXI4-S):

I am using Video In to AXI4-S IP to connect to the AXI4-S interface of HDMI Tx SS. I use VTC to generate native video timing (3840x2160 resolution) to the Video In to AXI4-S IP. Overflow is seen on this IP.

If both clocks in/out are running at 300MHz then it is likely that the overflow is due to the timing settings of the VTC or the Video in to AXI4-S IP not being able to transfer the data to the AXI4S bus fast enough.

Check 4 things. Put an ILA on the input and output of the stream to verify:

  1. Is your VTC set to the correct PPC and sending the correct timing for 3840x2160.
  2. Is the AXI4-S bus putting backpressure on the system or is tready high?
  3. Is the AXI4-S bus not transmitting data for large periods of time? (Tvalid going low for large periods)
  4. Look at the following beginner series.

    Video Beginner Series 7: How does the AXI4-Stream to Video Out IP work?

    Video Beginner Series 8: Debugging the AXI4-Stream to Video Out IP

What is the right way to handle overflow problem? Can I connect Video In to AXI4-S to  AXI4-S interface of HDMI Tx SS directly?

You can, but you need to make sure that they are running the same PPC (2/4) and that the HDMI core is ready to receive data. (Tready high)

Also, it appears that you are converting native video to AXI4-Stream, but this may not be needed. The HDMI core has the option for a native mode interface meaning that you would not need to convert your stream from native mode to AXI4-Stream. Please take a look at PG235.


Regards,

Sam

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Registered: ‎11-09-2015

Re: AXI video streaming protocol for HDMI Transmitter Subsystem v3.1 (Vivado 2018.3)

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HI yan-eng.ang@leica-microsystems.com ,

Do you have any updates on this topic? Were any of the replies from @watari or @samk helpful?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎12-25-2018

Re: AXI video streaming protocol for HDMI Transmitter Subsystem v3.1 (Vivado 2018.3)

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Hi Florent,

Sorry dealing with other issues now. Will come back to this problem later. Thanks.

 

Regards

YE

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Registered: ‎11-09-2015

Re: AXI video streaming protocol for HDMI Transmitter Subsystem v3.1 (Vivado 2018.3)

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Hi yan-eng.ang@leica-microsystems.com 

Did you look at back this?

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎12-25-2018

Re: AXI video streaming protocol for HDMI Transmitter Subsystem v3.1 (Vivado 2018.3)

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Hi Florent,

Not yet. Will close this issue for now. Thanks.

 

Regards

YE

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