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Explorer
Explorer
3,475 Views
Registered: ‎07-05-2017

AXI4-Stream to Video Out is not locked.

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AXI4s-Stream to Video Out is not generating any v and h sync nor any video data. I do see v and h sync and blanking signals being generated by the VTC and there is stream of video coming from the VDMA block all the way into the v_axi4s_vid_out_0 block. But no Video signals out to HDMI. Any ideas what I'm doing wrong? I'm using the vivado 2016.3 version.axi4s_stream_to_video_diagrma.JPGAxi4s_stream_to_video_ila.JPGAxi4s_stream_to_video_under_flow_ila.JPG. I see the the underflow is either high or pulsing.

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Moderator
Moderator
5,573 Views
Registered: ‎11-09-2015

Re: AXI4-Stream to Video Out is not locked.

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Hi @aynilian,

 

What is wrong is that you are in underflow. So you don't have enough data to have a good HDMI stream. Propably one of your IP is not giving enough data.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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7 Replies
Moderator
Moderator
5,574 Views
Registered: ‎11-09-2015

Re: AXI4-Stream to Video Out is not locked.

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Hi @aynilian,

 

What is wrong is that you are in underflow. So you don't have enough data to have a good HDMI stream. Propably one of your IP is not giving enough data.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Xilinx Employee
Xilinx Employee
3,450 Views
Registered: ‎08-02-2007

Re: AXI4-Stream to Video Out is not locked.

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If you have VDMA in the data path, please ensure AXI4-Stream to Video Out in master mode. For more details, please take a look at page 23 of https://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v4_0/pg044_v_axis_vid_out.pdf

Explorer
Explorer
3,439 Views
Registered: ‎07-05-2017

Re: AXI4-Stream to Video Out is not locked.

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Hi Xud,

 

The clocking was based on a Zedboard reference design for HDMI. The VDMA m_axis_mm2s_aclk and rest of the video processing blocks including the v_axi4s_video_out blocks are tied to FCLK_CLK1 (150 Mhz or 142.87..Mhz actual) The VTC is tied to a 148.5Mhz clock. Which kind of makes sense that the hsync and vsync are being generated faster than the stream coming in. I will try to connect the VDMA m_axis_mm2s_aclk and the following video stream to the same 148.5Mhz clock as the VTC. 

 

Also the v_axi4s_video_out Axi4s stream to Video block is configured as: Clock Mode -> Common,  Timing Mode: Master. 

 

See pictures below.

 

 

axi4s_stream_to_video_diagrma_clk.JPGaxi4s_stream_zynq_clk.JPGaxi4s_stream_to_video_diagrma3.JPG

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Explorer
Explorer
3,438 Views
Registered: ‎07-05-2017

Re: AXI4-Stream to Video Out is not locked.

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Hi florentw,

 

The VTC clock is 148.5 Mhz and the rest of the vido stream is clocked at actual clock rate of 142.87.. Mhz. This explains the underflow, but I thought the Axi4s stream to Video converter would accommodate the difference by re-transmitting the same line once in a while to match the clock differences. The clocking was based on an HDMI reference design for the Zedboard. I will reconnect the same clock for the VTC and Video Stream and post back my results.

 

Thanks!

Aynilian.

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Explorer
Explorer
3,430 Views
Registered: ‎07-05-2017

Re: AXI4-Stream to Video Out is not locked.

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Hi  

 

 

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Visitor azerty
Visitor
2,103 Views
Registered: ‎04-06-2018

Re: AXI4-Stream to Video Out is not locked.

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Hello every body

 

I have a problem witch can be similar to yourse but my block design is diffrent, can I get the testbench using to simulate your design? I write a testbench but I get somme errors so I can't simulate it.

thank youCapturemmmmmmmmmmmmmmmmmmmm.PNG

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Moderator
Moderator
2,034 Views
Registered: ‎11-09-2015

Re: AXI4-Stream to Video Out is not locked.

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Hi @azerty,

 

This is an old topic. Please create a new topic on the video board and other members could help you to solve the issue in you testbench.

 

Note: I am closing this topic for new replies

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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