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Contributor
Contributor
950 Views
Registered: ‎12-02-2016

AXI4-Stream to Video out can not locked without VDMA

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Hi,

I use HDMI Receiver Substem to receiver 1080p@60 (bpc=8,ppc=4). Its video out stream is connected to AXI4-Stream to Video Out directly( s_axis_video_aclk=200MHz). But the locked port is always low, and underflow port goes high occasionally. I then also add tpg between them and disable hdmi axi stream pass through, this time the video can get locked.

Some forum answer records said that vdma maybe needed to store frames, because the AXI4-Stream to Video Out needs time to achieve alginment, so I added vdma and the axi video stream can output correctly. I also added a FIFO with depth of 8196, but the AXI4-Stream to Video Out  cannot get locked at hits situation:

HDMI RxSS==>TPG==>FIFO==>AXI4-Stream to Video Out

I don't want to add DDR3 under cost consideration, and as s_axis_video_aclk is much higher than video out clk(200MHz vs. 148.5/4 MHz), so how can the HDMI Receiver Substem output under the control of AXI4-Stream to Video Out without VDMA?

Best Regards,
 

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1 Solution

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Moderator
Moderator
871 Views
Registered: ‎11-09-2015

Re: AXI4-Stream to Video out can not locked without VDMA

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Hi @xxhc417s,

The big advantage of the VDMA over the FIFO is that it can continue to read the previous frame if the next one is not available.

You might want to try to increase the size of your FIFO. But if you really want to avoid the VDMA, you might need to really investigate on the root cause. Add an ILA to see why you are waiting on data.

The reason why it is working when using the TPG is because the TPG can provide data during the blanking period. While for you HDMI input, blanking periods are...well...blanking periods, thus no data.

I would really recommend to use a VDMA. You might be able to use only internal memory with the VDMA, but it would be a big waste of resources.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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11 Replies
Scholar watari
Scholar
940 Views
Registered: ‎06-16-2013

Re: AXI4-Stream to Video out can not locked without VDMA

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Hi @xxhc417s

 

Would you share the value of status signal on "AXI4 Stream to Video out" IP ?

 

Best regards,

 

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Contributor
Contributor
897 Views
Registered: ‎12-02-2016

Re: AXI4-Stream to Video out can not locked without VDMA

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Hi, 

    Thank you for your response. The status is 0x03E8008F

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Moderator
Moderator
872 Views
Registered: ‎11-09-2015

Re: AXI4-Stream to Video out can not locked without VDMA

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Hi @xxhc417s,

The big advantage of the VDMA over the FIFO is that it can continue to read the previous frame if the next one is not available.

You might want to try to increase the size of your FIFO. But if you really want to avoid the VDMA, you might need to really investigate on the root cause. Add an ILA to see why you are waiting on data.

The reason why it is working when using the TPG is because the TPG can provide data during the blanking period. While for you HDMI input, blanking periods are...well...blanking periods, thus no data.

I would really recommend to use a VDMA. You might be able to use only internal memory with the VDMA, but it would be a big waste of resources.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Scholar watari
Scholar
839 Views
Registered: ‎06-16-2013

Re: AXI4-Stream to Video out can not locked without VDMA

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Hi @xxhc417s

 

According to status value, it points out that it is fine align, but  EOL is leading 1000[clk].

I'm probably sure that it seems transaction period issue.

I recommend to negate reset signal or to turn on enable at axi4stream to video out.

 

Best regards,

 

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Contributor
Contributor
826 Views
Registered: ‎12-02-2016

Re: AXI4-Stream to Video out can not locked without VDMA

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Hi,

I found a mismtach in an example program provided by Vivado. Now the AXI4-Stream to Video out can get locked for a time, and it has video output when connected to TV monitor, but the underflow still occurs at every 3~5 seconds.

It uses 100MHz clock as input clock, and can synthesis the clocks needed by video output clock. However the program doesn't update the new clock parameters before it attemps to check for the lock status, actually because the 100MHz input clock the block if(!lock){  } will never be executed, so the new clock can not be generated.

F:\Xilinx\SDK\2018.2\data\embeddedsw\XilinxProcessorIPLib\drivers\v_tpg_v8_0\examples\mian.c

VideoClockGen_WriteReg(0x200, clock_config_reg_0);
VideoClockGen_WriteReg(0x208, clock_config_reg_2);

usleep(300000);

lock = VideoClockGen_ReadReg(0x4) & 0x1;
if(!lock) //check for lock   //problem line
{
     //Video Clock Generator not locked
    VideoClockGen_WriteReg(0x25C, 0x7);
    VideoClockGen_WriteReg(0x25C, 0x2);
    timeout = 100000;
    while(!lock)
   {
        lock = VideoClockGen_ReadReg(0x4) & 0x1;
        --timeout;
       if(!timeout)
       {
           xil_printf("ERR:: Video Clock Generator failed lock\r\n");
         return(XST_FAILURE);
       }
  }
}

 

Scholar watari
Scholar
813 Views
Registered: ‎06-16-2013

Re: AXI4-Stream to Video out can not locked without VDMA

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Hi @xxhc417s

 

Would you share each actual clock frequency and actual fifo size ?

 

Best regards,

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Contributor
Contributor
804 Views
Registered: ‎12-02-2016

Re: AXI4-Stream to Video out can not locked without VDMA

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HDMI 2.0 Receiver Subsystem: 1024;

AXI-Stream Data FIFO: 2048

AXI-Stream to Video Out: 8192; Slave mode; vtg_ce conntects to gen_clken;

vid_io_out_clk = 148.5/4=37.125MHz, AXI-Stream clock=200MHz

 

Best Regards,

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Scholar watari
Scholar
799 Views
Registered: ‎06-16-2013

Re: AXI4-Stream to Video out can not locked without VDMA

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Hi @xxhc417s

 

I guess, is there your generated clock about 0.27[%] error ?

I recommend to make sure actual clock frequency. Not calculated clock frequency.

 

Or, would you share your PLL setting, if possible ?

 

Best regards,

 

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Contributor
Contributor
785 Views
Registered: ‎12-02-2016

Re: AXI4-Stream to Video out can not locked without VDMA

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Hi, @watari

The calculated clock frequency is the same as TPG example (main.c). Would you explain why my generated clock has about 0.27% error ?

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Moderator
Moderator
707 Views
Registered: ‎11-09-2015

Re: AXI4-Stream to Video out can not locked without VDMA

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HI @xxhc417s,

Do you have any updates on this? Were you able to have your project working without the VDMA?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
623 Views
Registered: ‎12-02-2016

Re: AXI4-Stream to Video out can not locked without VDMA

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Hi,

I deciced to use VDMA, now the project has finished. Thanks.

 

 

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