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Explorer
Explorer
1,133 Views
Registered: ‎10-31-2016

AXIS to Video SDI IP doestnot gice output with MIPI IP

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Hello, 

 

I tried example project with MIPI IP.

 

If I connect an AXIS to Video IP then There is not output signal i.e. video, vsync, hsync, data etc. I think it is because input is not in phase. 

 

Where as the TPG IP is enabled which is between the MIPI and AXIS to video IP then this AXIS to video IP starts giving output.

 

I would like to  how to solve it.

 

Best regards

 

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1 Solution

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Explorer
Explorer
958 Views
Registered: ‎10-31-2016

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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Now it works 

 

The module from pixle clock domain to PCIe clock domain was not working properly thats why there was issue with the pixels. 

 

Now it is stable and work without VDMA :) 

 

Thank you for help

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16 Replies
Xilinx Employee
Xilinx Employee
1,097 Views
Registered: ‎03-30-2016

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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Hello @msh

 

Your information is very limited and I cannot understand what you are trying to do with MIPI Example design, and what is the issue you are facing. Could you please elaborate more ?

It might help us a lot if you can add some pictures/block-diagrams on your issue description.

 

Thanks !

Example_Des.png
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Explorer
Explorer
1,094 Views
Registered: ‎10-31-2016

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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I remove VDMA from the chain and then add AXIS to video IP at broadcast. So that at one of the broadcast I can get SDI signals vsync, hsync, hblank, vblank, data and valid. 

 

But this donot work.

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Explorer
Explorer
1,085 Views
Registered: ‎10-31-2016

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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Can this pipeline work for 1 pixel mode with 594 Mhz for 4k ?

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Xilinx Employee
Xilinx Employee
1,062 Views
Registered: ‎03-30-2016

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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Hello @msh

 

I am not so clear with your design.

This MIPI example design created with dual-pixel configuration.

You will need to modify configuration of all modules if you want to use a single-pixel mode.

 

If the MIPI IP you are referring is the MIPI DSI TX.

You will need to modify the DSI timing register correctly to match the Video mode of your target display, before you can get any image on your display.

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Explorer
Explorer
1,056 Views
Registered: ‎10-31-2016

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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I am trying to use the same example with 2 pixel per clock. I did follwoing changes in the chain 

1. remove VDMA 

2. remove broadcast i.e. there is no HDMI or DSI connection.

3. connect AXIS to VIdeo directly to the TPG output (with reg slice between) 

 

but at the output of AXIS to Video IP, I dont see any signal. 

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Xilinx Employee
Xilinx Employee
1,023 Views
Registered: ‎03-30-2016

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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Hello @msh

 

XF_MSH_TEST.png

 

- I see. First this is not an issue of MIPI IP.

- If you remove VDMA to TPG connection, TPG do not have any timing-information input ,

   So the module will not be able to generate Video test-pattern.

 

Thanks & regards

 

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Explorer
Explorer
1,020 Views
Registered: ‎10-31-2016

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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Capture.PNG

 

I have connected the scaller directly to TPG 

Then I connect AXIS to video (slave mode) and Video timing controler

 

When I compile and test, I can see the video output from TPG but from sensor it is nothing. 

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Xilinx Employee
Xilinx Employee
1,005 Views
Registered: ‎03-30-2016

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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Hello @msh

1. Can you confirm if the default Example Design is working with your sensor ? Have you test it ?

2. If you think that MIPI CSI-2 RX is not working, could you please share the register dump ?

3. Why did you remove VDMA ?

4. Could you please compare the input of TPG before and after VDMA deletion ? Is the video-data input expected ?

 

Thanks !

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Explorer
Explorer
994 Views
Registered: ‎10-31-2016

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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I sound some more information 

 

I leave the VDMA and remove the HDMI 

 

then video out out works. I donto know why.

 

How does this VDMA helping ???  I am not able to understand.

 

 

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Moderator
Moderator
956 Views
Registered: ‎11-09-2015

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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HI @msh,

 

The VDMA is a frame buffer. It is helping if your input stream is not fast enough for your output stream.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Explorer
Explorer
951 Views
Registered: ‎10-31-2016

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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hi @florentw

 

I see the input to VDMA and output from the VDMA. It seems the hsync (tlast) and vsync(tuser) is calcualted in VDMA irrespective of input signal. Also output is continous pixel with continous valid high where as input to VDMA have non continuity. 

 

In my design the clock is same, hence output stream is working on same clock. I see the out frame, but every frame start shifting i.e. vsync is not proper without VDMA. 

 

I would like to avoide using DDR memory (saving memory bandwidth)

 

any suggestion how can I proceed..

 

Thanks 

 

Best regards 

Moderator
Moderator
947 Views
Registered: ‎11-09-2015

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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HI @msh,

 

The VDMA can also be used to convert the ppc (ex from 2pixel per clock to 1 pixel per clock (or other way)). This might be one of the reason you are having issue.

 

If it is only related to image not available, you can try to use an AXI4-Stream FIFO and see if it helps.

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Explorer
Explorer
944 Views
Registered: ‎10-31-2016

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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hi @florentw

 

thanks for the reply 

 

The input is 2ppc and output is also 2ppc. 

 

I tried with FIFO, but it doesnt work. 

 

any more option ?

 

Best regards 

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Explorer
Explorer
943 Views
Registered: ‎10-31-2016

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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Is there a test pattern generator to simulate MIPI output, so that I can verify the video processing chaing without VDMA ?

 

Best regards 

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Moderator
Moderator
940 Views
Registered: ‎11-09-2015

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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HI @msh,

 

I guess you are asking for a test bench (not test patter generator).

 

Xilinx does not provide any test bench for the MIPI DSI TX IP


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Explorer
Explorer
959 Views
Registered: ‎10-31-2016

Re: AXIS to Video SDI IP doestnot gice output with MIPI IP

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Now it works 

 

The module from pixle clock domain to PCIe clock domain was not working properly thats why there was issue with the pixels. 

 

Now it is stable and work without VDMA :) 

 

Thank you for help

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